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[/] [sparc64soc/] [trunk/] [Top/] [W1.v] - Blame information for rev 3

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Line No. Rev Author Line
1 2 dmitryr
`timescale 1ns / 1ps
2
//////////////////////////////////////////////////////////////////////////////////
3
// Company:  (C) Athree, 2009
4
// Engineer: Dmitry Rozhdestvenskiy 
5
// Email dmitry.rozhdestvenskiy@srisc.com dmitryr@a3.spb.ru divx4log@narod.ru
6
// 
7
// Design Name:    SPARC SoC single-core top level for Altera StratixIV devkit
8
// Module Name:    W1 
9
// Project Name:   SPARC SoC single-core
10
//
11
// LICENSE:
12
// This is a Free Hardware Design; you can redistribute it and/or
13
// modify it under the terms of the GNU General Public License
14
// version 2 as published by the Free Software Foundation.
15
// The above named program is distributed in the hope that it will
16
// be useful, but WITHOUT ANY WARRANTY; without even the implied
17
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18
// See the GNU General Public License for more details.
19
//
20
//////////////////////////////////////////////////////////////////////////////////
21
 
22
module W1(
23
 
24
   input         sysclk,
25
   input         sysrst,
26
 
27
   // ddr3 memory interface
28
   inout  [63:0] ddr3_dq,
29
   inout  [ 7:0] ddr3_dqs,
30
   inout  [ 7:0] ddr3_dqs_n,
31
   inout         ddr3_ck,
32
   inout         ddr3_ck_n,
33
   output        ddr3_reset,
34
   output [12:0] ddr3_a,
35
   output [ 2:0] ddr3_ba,
36
   output        ddr3_ras_n,
37
   output        ddr3_cas_n,
38
   output        ddr3_we_n,
39
   output        ddr3_cs_n,
40
   output        ddr3_odt,
41
   output        ddr3_ce,
42
   output [ 7:0] ddr3_dm,
43
 
44
   output        phy_init_done, // LED
45
   input         rup,
46
   input         rdn,
47
 
48
   // Console interface
49
   input  srx,
50
   output stx,
51
   input  [1:0] flash_rev,
52
 
53
   /* MII interface replaced by SGMII
54
 
55
   input        mtx_clk_pad_i,
56
   output [3:0] mtxd_pad_o,
57
   output       mtxen_pad_o,
58
   output       mtxerr_pad_o,
59
   input        mrx_clk_pad_i,
60
   input  [3:0] mrxd_pad_i,
61
   input        mrxdv_pad_i,
62
   input        mrxerr_pad_i,
63
   input        mcoll_pad_i,
64
   input        mcrs_pad_i, */
65
   output       mdc,
66
   inout        md,
67
 
68
   output eth_rst,
69
   output eth_tx,
70
   input  eth_rx,
71
 
72
   output led_10,
73
   output led_100,
74
   output led_1000,
75
   output led_link,
76
   output led_disp_err,
77
   output led_char_err,
78
   output led_an,
79
 
80
   output     [24:0] flash_addr,
81
   input      [15:0] flash_data,
82
   output            flash_oen,
83
   output            flash_wen,
84
   output            flash_cen,
85
   output            flash_clk,
86
   output            flash_adv,
87
   output            flash_rst
88
);
89
 
90
wire wb_rst_i;
91
wire [35:0] CONTROL0;
92
wire [35:0] CONTROL1;
93
wire [35:0] CONTROL2;
94
wire [1:0] VIO_SIG;
95
 
96
reg [31:0] cycle_count;
97
 
98
assign flash_clk=1;
99
assign flash_adv=0;
100
assign flash_rst=!wb_rst_i;
101
 
102
wire [63:0] m0_dat_i;
103
wire [63:0] m0_dat_o;
104
wire [63:0] m0_adr_i;
105
wire [ 7:0] m0_sel_i;
106
wire        m0_we_i;
107
wire        m0_cyc_i;
108
wire        m0_stb_i;
109
wire        m0_ack_o;
110
 
111
wire [63:0] m1_dat_i;
112
wire [63:0] m1_dat_o;
113
wire [63:0] m1_adr_i;
114
wire [ 7:0] m1_sel_i;
115
wire        m1_we_i;
116
wire        m1_cyc_i;
117
wire        m1_stb_i;
118
wire        m1_ack_o;
119
 
120
wire [63:0] s0_dat_i;
121
wire [63:0] s0_dat_o;
122
wire [63:0] s0_adr_o;
123
wire [ 7:0] s0_sel_o;
124
wire        s0_we_o;
125
wire        s0_cyc_o;
126
wire        s0_stb_o;
127
wire        s0_ack_i;
128
 
129
wire [63:0] s1_dat_i;
130
wire [63:0] s1_dat_o;
131
wire [63:0] s1_adr_o;
132
wire [ 7:0] s1_sel_o;
133
wire        s1_we_o;
134
wire        s1_cyc_o;
135
wire        s1_stb_o;
136
wire        s1_ack_i;
137
 
138
wire [63:0] s2_dat_i;
139
wire [63:0] s2_dat_o;
140
wire [63:0] s2_adr_o;
141
wire [ 7:0] s2_sel_o;
142
wire        s2_we_o;
143
wire        s2_cyc_o;
144
wire        s2_stb_o;
145
wire        s2_ack_i;
146
 
147
wire [63:0] s3_dat_i;
148
wire [63:0] s3_dat_o;
149
wire [63:0] s3_adr_o;
150
wire [ 7:0] s3_sel_o;
151
wire        s3_we_o;
152
wire        s3_cyc_o;
153
wire        s3_stb_o;
154
wire        s3_ack_i;
155
 
156
wire [63:0] s4_dat_i;
157
wire [63:0] s4_dat_o;
158
wire [63:0] s4_adr_o;
159
wire [ 7:0] s4_sel_o;
160
wire        s4_we_o;
161
wire        s4_cyc_o;
162
wire        s4_stb_o;
163
wire        s4_ack_i;
164
 
165
wb_conbus_top wishbone (
166
    .clk_i(wb_clk_i),
167
    .rst_i(wb_rst_i),
168
 
169
    //CPU
170
    .m0_dat_i(m0_dat_i),
171
    .m0_dat_o(m0_dat_o),
172
    .m0_adr_i(m0_adr_i),
173
    .m0_sel_i(m0_sel_i),
174
    .m0_we_i(m0_we_i),
175
    .m0_cyc_i(m0_cyc_i),
176
    .m0_stb_i(m0_stb_i),
177
    .m0_ack_o(m0_ack_o),
178
    .m0_err_o(),
179
    .m0_rty_o(),
180
    .m0_cab_i(0),
181
 
182
    //Ethernet
183
    .m1_dat_i(m1_dat_i),
184
    .m1_dat_o(m1_dat_o),
185
    .m1_adr_i(m1_adr_i),
186
    .m1_sel_i(m1_sel_i),
187
    .m1_we_i(m1_we_i),
188
    .m1_cyc_i(m1_cyc_i),
189
    .m1_stb_i(m1_stb_i),
190
    .m1_ack_o(m1_ack_o),
191
    .m1_err_o(m1_err_o),
192
    .m1_rty_o(m1_rty_o),
193
    .m1_cab_i(m1_cab_i),
194
 
195
    .m2_dat_i(0),
196
    .m2_dat_o(),
197
    .m2_adr_i(0),
198
    .m2_sel_i(0),
199
    .m2_we_i(0),
200
    .m2_cyc_i(0),
201
    .m2_stb_i(0),
202
    .m2_ack_o(),
203
    .m2_err_o(),
204
    .m2_rty_o(),
205
    .m2_cab_i(0),
206
 
207
    .m3_dat_i(0),
208
    .m3_dat_o(),
209
    .m3_adr_i(0),
210
    .m3_sel_i(0),
211
    .m3_we_i(0),
212
    .m3_cyc_i(0),
213
    .m3_stb_i(0),
214
    .m3_ack_o(),
215
    .m3_err_o(),
216
    .m3_rty_o(),
217
    .m3_cab_i(0),
218
 
219
    .m4_dat_i(0),
220
    .m4_dat_o(),
221
    .m4_adr_i(0),
222
    .m4_sel_i(0),
223
    .m4_we_i(0),
224
    .m4_cyc_i(0),
225
    .m4_stb_i(0),
226
    .m4_ack_o(),
227
    .m4_err_o(),
228
    .m4_rty_o(),
229
    .m4_cab_i(0),
230
 
231
    .m5_dat_i(0),
232
    .m5_dat_o(),
233
    .m5_adr_i(0),
234
    .m5_sel_i(0),
235
    .m5_we_i(0),
236
    .m5_cyc_i(0),
237
    .m5_stb_i(0),
238
    .m5_ack_o(),
239
    .m5_err_o(),
240
    .m5_rty_o(),
241
    .m5_cab_i(0),
242
 
243
    .m6_dat_i(0),
244
    .m6_dat_o(),
245
    .m6_adr_i(0),
246
    .m6_sel_i(0),
247
    .m6_we_i(0),
248
    .m6_cyc_i(0),
249
    .m6_stb_i(0),
250
    .m6_ack_o(),
251
    .m6_err_o(),
252
    .m6_rty_o(),
253
    .m6_cab_i(0),
254
 
255
    .m7_dat_i(0),
256
    .m7_dat_o(),
257
    .m7_adr_i(0),
258
    .m7_sel_i(0),
259
    .m7_we_i(0),
260
    .m7_cyc_i(0),
261
    .m7_stb_i(0),
262
    .m7_ack_o(),
263
    .m7_err_o(),
264
    .m7_rty_o(),
265
    .m7_cab_i(0),
266
 
267
    //DRAM
268
    .s0_dat_i(s0_dat_i),
269
    .s0_dat_o(s0_dat_o),
270
    .s0_adr_o(s0_adr_o),
271
    .s0_sel_o(s0_sel_o),
272
    .s0_we_o(s0_we_o),
273
    .s0_cyc_o(s0_cyc_o),
274
    .s0_stb_o(s0_stb_o),
275
    .s0_ack_i(s0_ack_i),
276
    .s0_err_i(0),
277
    .s0_rty_i(0),
278
    .s0_cab_o(),
279
 
280
    //Flash
281
    .s1_dat_i(s1_dat_i),
282
    .s1_dat_o(s1_dat_o),
283
    .s1_adr_o(s1_adr_o),
284
    .s1_sel_o(s1_sel_o),
285
    .s1_we_o(s1_we_o),
286
    .s1_cyc_o(s1_cyc_o),
287
    .s1_stb_o(s1_stb_o),
288
    .s1_ack_i(s1_ack_i),
289
    .s1_err_i(s1_err_i),
290
    .s1_rty_i(s1_rty_i),
291
    .s1_cab_o(s1_cab_o),
292
 
293
    //Ethernet
294
    .s2_dat_i(s2_dat_i),
295
    .s2_dat_o(s2_dat_o),
296
    .s2_adr_o(s2_adr_o),
297
    .s2_sel_o(s2_sel_o),
298
    .s2_we_o(s2_we_o),
299
    .s2_cyc_o(s2_cyc_o),
300
    .s2_stb_o(s2_stb_o),
301
    .s2_ack_i(s2_ack_i),
302
    .s2_err_i(s2_err_i),
303
    .s2_rty_i(s2_rty_i),
304
    .s2_cab_o(s2_cab_o),
305
 
306
    //UART
307
    .s3_dat_i({s3_dat_i[31:0],s3_dat_i[31:0]}),
308
    .s3_dat_o(s3_dat_o),
309
    .s3_adr_o(s3_adr_o),
310
    .s3_sel_o(s3_sel_o),
311
    .s3_we_o(s3_we_o),
312
    .s3_cyc_o(s3_cyc_o),
313
    .s3_stb_o(s3_stb_o),
314
    .s3_ack_i(s3_ack_i),
315
    .s3_err_i(s3_err_i),
316
    .s3_rty_i(s3_rty_i),
317
    .s3_cab_o(s3_cab_o),
318
 
319
    //Second flash interface for fff8xxxxxx ram disk addressing
320
    .s4_dat_i(s4_dat_i),
321
    .s4_dat_o(s4_dat_o),
322
    .s4_adr_o(s4_adr_o),
323
    .s4_sel_o(s4_sel_o),
324
    .s4_we_o(s4_we_o),
325
    .s4_cyc_o(s4_cyc_o),
326
    .s4_stb_o(s4_stb_o),
327
    .s4_ack_i(s4_ack_i),
328
    .s4_err_i(s4_err_i),
329
    .s4_rty_i(s4_rty_i),
330
    .s4_cab_o(s4_cab_o),
331
 
332
    .s5_dat_i(0),
333
    .s5_dat_o(),
334
    .s5_adr_o(),
335
    .s5_sel_o(),
336
    .s5_we_o(),
337
    .s5_cyc_o(),
338
    .s5_stb_o(),
339
    .s5_ack_i(0),
340
    .s5_err_i(0),
341
    .s5_rty_i(0),
342
    .s5_cab_o(),
343
 
344
    .s6_dat_i(0),
345
    .s6_dat_o(),
346
    .s6_adr_o(),
347
    .s6_sel_o(),
348
    .s6_we_o(),
349
    .s6_cyc_o(),
350
    .s6_stb_o(),
351
    .s6_ack_i(0),
352
    .s6_err_i(0),
353
    .s6_rty_i(0),
354
    .s6_cab_o(),
355
 
356
    .s7_dat_i(0),
357
    .s7_dat_o(),
358
    .s7_adr_o(),
359
    .s7_sel_o(),
360
    .s7_we_o(),
361
    .s7_cyc_o(),
362
    .s7_stb_o(),
363
    .s7_ack_i(0),
364
    .s7_err_i(0),
365
    .s7_rty_i(0),
366
    .s7_cab_o()
367
);
368
 
369
s1_top cpu (
370
    .sys_clock_i(wb_clk_i),
371
    .sys_reset_i(wb_rst_i),
372 3 dmitryr
    .eth_irq_i(eth_irq),
373 2 dmitryr
    .wbm_ack_i(m0_ack_o),
374
    .wbm_data_i(m0_dat_o),
375
    .wbm_cycle_o(m0_cyc_i),
376
    .wbm_strobe_o(m0_stb_i),
377
    .wbm_we_o(m0_we_i),
378
    .wbm_addr_o(m0_adr_i),
379
    .wbm_data_o(m0_dat_i),
380
    .wbm_sel_o(m0_sel_i)
381
    );
382
 
383 3 dmitryr
wire [7:0] fifo_used;
384
 
385 2 dmitryr
dram_wb dram_wb_inst (
386
    .clk200(sysclk),
387
    .rup(rup),
388
    .rdn(rdn),
389
    .wb_clk_i(wb_clk_i),
390
    .wb_rst_i(wb_rst_i),
391
    .wb_dat_i(s0_dat_o),
392
    .wb_dat_o(s0_dat_i),
393
    .wb_adr_i(s0_adr_o),
394
    .wb_sel_i(s0_sel_o),
395
    .wb_we_i(s0_we_o),
396
    .wb_cyc_i(s0_cyc_o),
397
    .wb_stb_i(s0_stb_o),
398
    .wb_ack_o(s0_ack_i),
399
    .wb_err_o(s0_err_i),
400
    .wb_rty_o(s0_rty_i),
401
    .wb_cab_i(s0_cab_o),
402
    .ddr3_dq(ddr3_dq),
403
    .ddr3_dqs(ddr3_dqs),
404
    .ddr3_dqs_n(ddr3_dqs_n),
405
    .ddr3_ck(ddr3_ck),
406
    .ddr3_ck_n(ddr3_ck_n),
407
    .ddr3_reset(ddr3_reset),
408
    .ddr3_a(ddr3_a),
409
    .ddr3_ba(ddr3_ba),
410
    .ddr3_ras_n(ddr3_ras_n),
411
    .ddr3_cas_n(ddr3_cas_n),
412
    .ddr3_we_n(ddr3_we_n),
413
    .ddr3_cs_n(ddr3_cs_n),
414
    .ddr3_odt(ddr3_odt),
415
    .ddr3_ce(ddr3_ce),
416
    .ddr3_dm(ddr3_dm),
417
    .phy_init_done(phy_init_done),
418
    .dcm_locked(dcm_locked),
419 3 dmitryr
    .fifo_used(fifo_used),
420 2 dmitryr
    .sysrst(sysrst)
421
);
422
 
423
WBFLASH flash (
424
    .wb_clk_i(wb_clk_i),
425
    .wb_rst_i(wb_rst_i),
426
 
427
    .wb_dat_i(s1_dat_o),
428
    .wb_dat_o(s1_dat_i),
429
    .wb_adr_i(s1_adr_o),
430
    .wb_sel_i(s1_sel_o),
431
    .wb_we_i(s1_we_o),
432
    .wb_cyc_i(s1_cyc_o),
433
    .wb_stb_i(s1_stb_o),
434
    .wb_ack_o(s1_ack_i),
435
    .wb_err_o(s1_err_i),
436
    .wb_rty_o(s1_rty_i),
437
    .wb_cab_i(s1_cab_o),
438
 
439
    .wb1_dat_i(s4_dat_o),
440
    .wb1_dat_o(s4_dat_i),
441
    .wb1_adr_i(s4_adr_o),
442
    .wb1_sel_i(s4_sel_o),
443
    .wb1_we_i(s4_we_o),
444
    .wb1_cyc_i(s4_cyc_o),
445
    .wb1_stb_i(s4_stb_o),
446
    .wb1_ack_o(s4_ack_i),
447
    .wb1_err_o(s4_err_i),
448
    .wb1_rty_o(s4_rty_i),
449
    .wb1_cab_i(s4_cab_o),
450
 
451
    .flash_addr(flash_addr),
452
    .flash_data(flash_data),
453
    .flash_oen(flash_oen),
454
    .flash_wen(flash_wen),
455
    .flash_cen(flash_cen),
456
    .flash_rev(flash_rev)
457
);
458
 
459
uart_top uart16550 (
460
    .wb_clk_i(wb_clk_i),
461
    .wb_rst_i(wb_rst_i),
462
    .wb_adr_i({s3_adr_o[4:3],s3_sel_o[3:0]==4'h0 ? 1'b0:1'b1,2'b00}),
463
    .wb_dat_i(s3_sel_o[3:0]==4'h0 ? {s3_dat_o[39:32],s3_dat_o[47:40],s3_dat_o[55:48],s3_dat_o[63:56]}:{s3_dat_o[7:0],s3_dat_o[15:8],s3_dat_o[23:16],s3_dat_o[31:24]}),
464
    .wb_dat_o({s3_dat_i[7:0],s3_dat_i[15:8],s3_dat_i[23:16],s3_dat_i[31:24]}),
465
    .wb_we_i(s3_we_o),
466
    .wb_stb_i(s3_stb_o),
467
    .wb_cyc_i(s3_cyc_o),
468
    .wb_ack_o(s3_ack_i),
469
    .wb_sel_i(s3_sel_o[3:0]==4'h0 ? {s3_sel_o[4],s3_sel_o[5],s3_sel_o[6],s3_sel_o[7]}:{s3_sel_o[0],s3_sel_o[1],s3_sel_o[2],s3_sel_o[3]}), // Big endian 
470
    .int_o(int_o),
471
    .stx_pad_o(stx),
472
    .srx_pad_i(srx),
473
    .rts_pad_o(),
474
    .cts_pad_i(1),
475
    .dtr_pad_o(),
476
    .dsr_pad_i(1),
477
    .ri_pad_i(0),
478
    .dcd_pad_i(1),
479
         .baud_o(baud_o)
480
);
481
 
482
eth_sgmii eth_ctrl (
483
    .wb_clk_i(wb_clk_i),
484
    .wb_rst_i(wb_rst_i),
485
    .sysclk(sysclk),
486
 
487
    .wb_dat_i(s2_dat_o),
488
    .wb_dat_o(s2_dat_i),
489
    .wb_adr_i(s2_adr_o),
490
    .wb_sel_i(s2_sel_o),
491
    .wb_we_i(s2_we_o),
492
    .wb_cyc_i(s2_cyc_o),
493
    .wb_stb_i(s2_stb_o),
494
    .wb_ack_o(s2_ack_i),
495
    .wb_err_o(s2_err_i),
496
 
497
    .m_wb_adr_o(m1_adr_i),
498
    .m_wb_sel_o(m1_sel_i),
499
    .m_wb_we_o(m1_we_i),
500
    .m_wb_dat_o(m1_dat_i),
501
    .m_wb_dat_i(m1_dat_o),
502
    .m_wb_cyc_o(m1_cyc_i),
503
    .m_wb_stb_o(m1_stb_i),
504
    .m_wb_ack_i(m1_ack_o),
505
    .m_wb_err_i(m1_err_o),
506
 
507
    .sgmii_tx(eth_tx),
508
    .sgmii_rx(eth_rx),
509
    .led_10(led_10),
510
    .led_100(led_100),
511
    .led_1000(led_1000),
512
    .led_an(led_an),
513
    .led_disp_err(led_disp_err),
514
    .led_char_err(led_char_err),
515
    .led_link(led_link),
516
 
517
    .md(md),
518
    .mdc(mdc),
519
 
520 3 dmitryr
    .int_eth(eth_int)
521 2 dmitryr
);
522
 
523
assign eth_rst=!wb_rst_i; // PHY reset
524
 
525
wire sysrst_p;
526
assign sysrst_p=!sysrst;
527
 
528
// Standard PLL
529
pll pll_inst(
530
        .areset(sysrst_p),
531
        .inclk0(sysclk),
532
        .c0(wb_clk_i), //Up to 75 MHz on Stratix IV
533
        .locked(dcm_locked)
534
);
535
 
536
assign wb_rst_i=(!dcm_locked || !phy_init_done);
537
 
538
reg [223:0] ILA_DATA;
539
 
540
/*
541
[63:0]    address
542
[127:64]  data to core
543
[191:128] data from core
544
[199:192] sel
545
[200]     cyc
546
[201]     stb
547
[202]     we
548
[203]     ack
549
*/
550
 
551
// SignalTap II
552
ST ila(
553
        .acq_clk(wb_clk_i),
554
        .acq_data_in(ILA_DATA),
555
        .acq_trigger_in(ILA_DATA),
556
        .storage_enable(ILA_DATA[203]) // wb_ack
557
);
558
 
559
// InSystem Sources
560
VIO vio_inst(
561
        .probe(0),
562
        .source_clk(wb_clk_i),
563
        .source(VIO_SIG)
564
);
565
 
566
always @(posedge wb_clk_i or posedge wb_rst_i)
567
   if(wb_rst_i)
568
           cycle_count<=0;
569
        else
570
           cycle_count<=cycle_count+1;
571
 
572
always @( * )
573
   begin
574
      case(VIO_SIG)
575
         2'b00:
576
            begin
577
               ILA_DATA[63:0]<=m0_adr_i;
578
               ILA_DATA[127:64]<=m0_dat_o;
579
               ILA_DATA[191:128]<=m0_dat_i;
580
               ILA_DATA[199:192]<=m0_sel_i;
581
               ILA_DATA[200]<=m0_cyc_i;
582
               ILA_DATA[201]<=m0_stb_i;
583
               ILA_DATA[202]<=m0_we_i;
584
               ILA_DATA[203]<=m0_ack_o;
585
            end
586
         2'b01:
587
            begin
588
               ILA_DATA[63:0]<=m1_adr_i;
589
               ILA_DATA[127:64]<=m1_dat_o;
590
               ILA_DATA[191:128]<=m1_dat_i;
591
               ILA_DATA[199:192]<=m1_sel_i;
592
               ILA_DATA[200]<=m1_cyc_i;
593
               ILA_DATA[201]<=m1_stb_i;
594
               ILA_DATA[202]<=m1_we_i;
595
               ILA_DATA[203]<=m1_ack_o;
596
            end
597
         2'b10:
598
            begin
599
               ILA_DATA[63:0]<=s2_adr_o;
600
               ILA_DATA[127:64]<=s2_dat_o;
601
               ILA_DATA[191:128]<=s2_dat_i;
602
               ILA_DATA[199:192]<=s2_sel_o;
603
               ILA_DATA[200]<=s2_cyc_o;
604
               ILA_DATA[201]<=s2_stb_o;
605
               ILA_DATA[202]<=s2_we_o;
606
               ILA_DATA[203]<=s2_ack_i;
607
            end
608
         2'b11:
609
            begin
610
               ILA_DATA[63:0]<=s4_adr_o;
611
               ILA_DATA[127:64]<=s4_dat_o;
612
               ILA_DATA[191:128]<=s4_dat_i;
613
               ILA_DATA[199:192]<=s4_sel_o;
614
               ILA_DATA[200]<=s4_cyc_o;
615
               ILA_DATA[201]<=s4_stb_o;
616
               ILA_DATA[202]<=s4_we_o;
617
               ILA_DATA[203]<=s4_ack_i;
618
            end
619
      endcase
620 3 dmitryr
      ILA_DATA[204]<=stx;
621
      ILA_DATA[205]<=srx;
622
      ILA_DATA[206]<=baud_o;
623
      //ILA_DATA[220:207]<=cycle_count[31:18];
624
      ILA_DATA[220:213]<=fifo_used;
625
      ILA_DATA[212:207]<=cycle_count[31:26];
626 2 dmitryr
      ILA_DATA[221]<=dcm_locked;
627
      ILA_DATA[222]<=wb_rst_i;
628
      ILA_DATA[223]<=phy_init_done;
629
   end
630
 
631
endmodule

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