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[/] [spdif_transmitter/] [trunk/] [rtl/] [spdif_core.v] - Blame information for rev 3

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//-----------------------------------------------------------------
//                        SPDIF Transmitter
//                              V0.1
//                        Ultra-Embedded.com
//                          Copyright 2012
//
//                 Email: admin@ultra-embedded.com
//
//                         License: GPL
// If you would like a version with a more permissive license for
// use in closed source commercial applications please contact me
// for details.
//-----------------------------------------------------------------
//
// This file is open source HDL; you can redistribute it and/or 
// modify it under the terms of the GNU General Public License as 
// published by the Free Software Foundation; either version 2 of 
// the License, or (at your option) any later version.
//
// This file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public 
// License along with this file; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
// USA
//-----------------------------------------------------------------
module spdif_core
(
    input           clk_i,
    input           rst_i,
 
    // SPDIF bit output enable
    // Single cycle pulse synchronous to clk_i which drives
    // the output bit rate.
    // For 44.1KHz, 44100×32×2×2 = 5,644,800Hz
    // For 48KHz,   48000×32×2×2 = 6,144,000Hz
    input           bit_out_en_i,
 
    // Output
    output          spdif_o,
 
    // Audio interface (16-bit x 2 = RL)
    input [31:0]    sample_i,
    output reg      sample_req_o
);
 
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
reg [15:0]  audio_sample_q;
reg [8:0]   subframe_count_q;
 
reg         load_subframe_q;
reg [7:0]   preamble_q;
wire [31:0] subframe_w;
 
reg [5:0]   bit_count_q;
reg         bit_toggle_q;
 
// Xilinx: Place output flop in IOB
//synthesis attribute IOB of spdif_out_q is "TRUE"
reg         spdif_out_q;
 
reg [5:0]   parity_count_q;
 
//-----------------------------------------------------------------
// Subframe Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
    if (rst_i == 1'b1)
        subframe_count_q    <= 9'd0;
    else if (load_subframe_q)
    begin
        // 192 frames (384 subframes) in an audio block
        if (subframe_count_q == 9'd383)
            subframe_count_q <= 9'd0;
        else
            subframe_count_q <= subframe_count_q + 9'd1;
    end
end
 
//-----------------------------------------------------------------
// Sample capture
//-----------------------------------------------------------------
reg [15:0] sample_buf_q;
 
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        audio_sample_q      <= 16'h0000;
        sample_buf_q        <= 16'h0000;
        sample_req_o        <= 1'b0;
   end
   else if (load_subframe_q)
   begin
        // Start of frame (first subframe)?
        if (subframe_count_q[0] == 1'b0)
        begin
            // Use left sample
            audio_sample_q <= sample_i[15:0];
 
            // Store right sample
            sample_buf_q <= sample_i[31:16];
 
            // Request next sample
            sample_req_o <= 1'b1;
        end
        else
        begin
            // Use right sample
            audio_sample_q <= sample_buf_q;
 
            sample_req_o <= 1'b0;
        end
   end
   else
        sample_req_o <= 1'b0;
end
 
// Timeslots 3 - 0 = Preamble
assign subframe_w[3:0] = 4'b0000;
 
// Timeslots 7 - 4 = 24-bit audio LSB
assign subframe_w[7:4] = 4'b0000;
 
// Timeslots 11 - 8 = 20-bit audio LSB
assign subframe_w[11:8] = 4'b0000;
 
// Timeslots 27 - 12 = 16-bit audio
assign subframe_w[27:12] = audio_sample_q;
 
// Timeslots 28 = Validity
assign subframe_w[28] = 1'b0; // Valid
 
// Timeslots 29 = User bit
assign subframe_w[29] = 1'b0;
 
// Timeslots 30 = Channel status bit
assign subframe_w[30] = 1'b0;
 
// Timeslots 31 = Even Parity bit (31:4)
assign subframe_w[31] = 1'b0;
 
//-----------------------------------------------------------------
// Preamble
//-----------------------------------------------------------------
localparam PREAMBLE_Z = 8'b00010111;
localparam PREAMBLE_Y = 8'b00100111;
localparam PREAMBLE_X = 8'b01000111;
 
reg [7:0] preamble_r;
 
always @ *
begin
    // Start of audio block?
    // Z(B) - Left channel
    if (subframe_count_q == 9'd0)
        preamble_r = PREAMBLE_Z; // Z(B)
    // Right Channel?
    else if (subframe_count_q[0] == 1'b1)
        preamble_r = PREAMBLE_Y; // Y(W)
    // Left Channel (but not start of block)?
    else
        preamble_r = PREAMBLE_X; // X(M)
end
 
always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
    preamble_q  <= 8'h00;
else if (load_subframe_q)
    preamble_q  <= preamble_r;
 
//-----------------------------------------------------------------
// Parity Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
begin
   if (rst_i == 1'b1)
   begin
        parity_count_q  <= 6'd0;
   end
   // Time to output a bit?
   else if (bit_out_en_i)
   begin
        // Preamble bits?
        if (bit_count_q < 6'd8)
        begin
            parity_count_q  <= 6'd0;
        end
        // Normal timeslots
        else if (bit_count_q < 6'd62)
        begin
            // On first pass through this timeslot, count number of high bits
            if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)
                parity_count_q <= parity_count_q + 6'd1;
        end
   end
end
 
//-----------------------------------------------------------------
// Bit Counter
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
begin
    if (rst_i == 1'b1)
    begin
        bit_count_q     <= 6'b0;
        load_subframe_q <= 1'b1;
    end
    // Time to output a bit?
    else if (bit_out_en_i)
    begin
        // 32 timeslots (x2 for double frequency)
        if (bit_count_q == 6'd63)
        begin
            bit_count_q     <= 6'd0;
            load_subframe_q <= 1'b1;
        end
        else
        begin
            bit_count_q     <= bit_count_q + 6'd1;
            load_subframe_q <= 1'b0;
        end
    end
    else
        load_subframe_q <= 1'b0;
end
 
//-----------------------------------------------------------------
// Bit half toggle
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i)
if (rst_i == 1'b1)
    bit_toggle_q    <= 1'b0;
// Time to output a bit?
else if (bit_out_en_i)
    bit_toggle_q <= ~bit_toggle_q;
 
//-----------------------------------------------------------------
// Output bit (BMC encoded)
//-----------------------------------------------------------------
reg bit_r;
 
always @ *
begin
    bit_r = spdif_out_q;
 
    // Time to output a bit?
    if (bit_out_en_i)
    begin
        // Preamble bits?
        if (bit_count_q < 6'd8)
        begin
            bit_r = preamble_q[bit_count_q[2:0]];
        end
        // Normal timeslots
        else if (bit_count_q < 6'd62)
        begin
            if (subframe_w[bit_count_q / 2] == 1'b0)
            begin
                if (bit_toggle_q == 1'b0)
                    bit_r = ~spdif_out_q;
                else
                    bit_r = spdif_out_q;
            end
            else
                bit_r = ~spdif_out_q;
        end
        // Parity timeslot
        else
        begin
            // Even number of high bits, make odd
            if (parity_count_q[0] == 1'b0)
            begin
                if (bit_toggle_q == 1'b0)
                    bit_r = ~spdif_out_q;
                else
                    bit_r = spdif_out_q;
            end
            else
                bit_r = ~spdif_out_q;
        end
    end
end
 
always @ (posedge rst_i or posedge clk_i )
if (rst_i == 1'b1)
    spdif_out_q <= 1'b0;
else
    spdif_out_q <= bit_r;
 
assign spdif_o  = spdif_out_q;
 
endmodule

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Subversion Repositories spdif_transmitter

[/] [spdif_transmitter/] [trunk/] [rtl/] [spdif_core.v] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	ultra_embe	`//-----------------------------------------------------------------`
2			`// SPDIF Transmitter`
3			`// V0.1`
4			`// Ultra-Embedded.com`
5			`// Copyright 2012`
6			`//`
7			`// Email: admin@ultra-embedded.com`
8			`//`
9			`// License: GPL`
10			`// If you would like a version with a more permissive license for`
11			`// use in closed source commercial applications please contact me`
12			`// for details.`
13			`//-----------------------------------------------------------------`
14			`//`
15			`// This file is open source HDL; you can redistribute it and/or`
16			`// modify it under the terms of the GNU General Public License as`
17			`// published by the Free Software Foundation; either version 2 of`
18			`// the License, or (at your option) any later version.`
19			`//`
20			`// This file is distributed in the hope that it will be useful,`
21			`// but WITHOUT ANY WARRANTY; without even the implied warranty of`
22			`// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
23			`// GNU General Public License for more details.`
24			`//`
25			`// You should have received a copy of the GNU General Public`
26			`// License along with this file; if not, write to the Free Software`
27			`// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307`
28			`// USA`
29			`//-----------------------------------------------------------------`
30			`module spdif_core`
31			`(`
32			`input clk_i,`
33			`input rst_i,`
34
35			`// SPDIF bit output enable`
36			`// Single cycle pulse synchronous to clk_i which drives`
37			`// the output bit rate.`
38			`// For 44.1KHz, 44100×32×2×2 = 5,644,800Hz`
39			`// For 48KHz, 48000×32×2×2 = 6,144,000Hz`
40			`input bit_out_en_i,`
41
42			`// Output`
43			`output spdif_o,`
44
45			`// Audio interface (16-bit x 2 = RL)`
46			`input [31:0] sample_i,`
47			`output reg sample_req_o`
48			`);`
49
50			`//-----------------------------------------------------------------`
51			`// Registers`
52			`//-----------------------------------------------------------------`
53			`reg [15:0] audio_sample_q;`
54			`reg [8:0] subframe_count_q;`
55
56			`reg load_subframe_q;`
57			`reg [7:0] preamble_q;`
58			`wire [31:0] subframe_w;`
59
60			`reg [5:0] bit_count_q;`
61			`reg bit_toggle_q;`
62
63			`// Xilinx: Place output flop in IOB`
64			`//synthesis attribute IOB of spdif_out_q is "TRUE"`
65			`reg spdif_out_q;`
66
67			`reg [5:0] parity_count_q;`
68
69			`//-----------------------------------------------------------------`
70			`// Subframe Counter`
71			`//-----------------------------------------------------------------`
72			`always @ (posedge rst_i or posedge clk_i )`
73			`begin`
74			`if (rst_i == 1'b1)`
75			`subframe_count_q <= 9'd0;`
76			`else if (load_subframe_q)`
77			`begin`
78			`// 192 frames (384 subframes) in an audio block`
79			`if (subframe_count_q == 9'd383)`
80			`subframe_count_q <= 9'd0;`
81			`else`
82			`subframe_count_q <= subframe_count_q + 9'd1;`
83			`end`
84			`end`
85
86			`//-----------------------------------------------------------------`
87			`// Sample capture`
88			`//-----------------------------------------------------------------`
89			`reg [15:0] sample_buf_q;`
90
91			`always @ (posedge rst_i or posedge clk_i )`
92			`begin`
93			`if (rst_i == 1'b1)`
94			`begin`
95			`audio_sample_q <= 16'h0000;`
96			`sample_buf_q <= 16'h0000;`
97			`sample_req_o <= 1'b0;`
98			`end`
99			`else if (load_subframe_q)`
100			`begin`
101			`// Start of frame (first subframe)?`
102			`if (subframe_count_q[0] == 1'b0)`
103			`begin`
104			`// Use left sample`
105			`audio_sample_q <= sample_i[15:0];`
106
107			`// Store right sample`
108			`sample_buf_q <= sample_i[31:16];`
109
110			`// Request next sample`
111			`sample_req_o <= 1'b1;`
112			`end`
113			`else`
114			`begin`
115			`// Use right sample`
116			`audio_sample_q <= sample_buf_q;`
117
118			`sample_req_o <= 1'b0;`
119			`end`
120			`end`
121			`else`
122			`sample_req_o <= 1'b0;`
123			`end`
124
125			`// Timeslots 3 - 0 = Preamble`
126			`assign subframe_w[3:0] = 4'b0000;`
127
128			`// Timeslots 7 - 4 = 24-bit audio LSB`
129			`assign subframe_w[7:4] = 4'b0000;`
130
131			`// Timeslots 11 - 8 = 20-bit audio LSB`
132			`assign subframe_w[11:8] = 4'b0000;`
133
134			`// Timeslots 27 - 12 = 16-bit audio`
135			`assign subframe_w[27:12] = audio_sample_q;`
136
137			`// Timeslots 28 = Validity`
138			`assign subframe_w[28] = 1'b0; // Valid`
139
140			`// Timeslots 29 = User bit`
141			`assign subframe_w[29] = 1'b0;`
142
143			`// Timeslots 30 = Channel status bit`
144			`assign subframe_w[30] = 1'b0;`
145
146			`// Timeslots 31 = Even Parity bit (31:4)`
147			`assign subframe_w[31] = 1'b0;`
148
149			`//-----------------------------------------------------------------`
150			`// Preamble`
151			`//-----------------------------------------------------------------`
152			`localparam PREAMBLE_Z = 8'b00010111;`
153			`localparam PREAMBLE_Y = 8'b00100111;`
154			`localparam PREAMBLE_X = 8'b01000111;`
155
156			`reg [7:0] preamble_r;`
157
158			`always @ *`
159			`begin`
160			`// Start of audio block?`
161			`// Z(B) - Left channel`
162			`if (subframe_count_q == 9'd0)`
163			`preamble_r = PREAMBLE_Z; // Z(B)`
164			`// Right Channel?`
165			`else if (subframe_count_q[0] == 1'b1)`
166			`preamble_r = PREAMBLE_Y; // Y(W)`
167			`// Left Channel (but not start of block)?`
168			`else`
169			`preamble_r = PREAMBLE_X; // X(M)`
170			`end`
171
172			`always @ (posedge rst_i or posedge clk_i )`
173			`if (rst_i == 1'b1)`
174			`preamble_q <= 8'h00;`
175			`else if (load_subframe_q)`
176			`preamble_q <= preamble_r;`
177
178			`//-----------------------------------------------------------------`
179			`// Parity Counter`
180			`//-----------------------------------------------------------------`
181			`always @ (posedge rst_i or posedge clk_i )`
182			`begin`
183			`if (rst_i == 1'b1)`
184			`begin`
185			`parity_count_q <= 6'd0;`
186			`end`
187			`// Time to output a bit?`
188			`else if (bit_out_en_i)`
189			`begin`
190			`// Preamble bits?`
191			`if (bit_count_q < 6'd8)`
192			`begin`
193			`parity_count_q <= 6'd0;`
194			`end`
195			`// Normal timeslots`
196			`else if (bit_count_q < 6'd62)`
197			`begin`
198			`// On first pass through this timeslot, count number of high bits`
199			`if (bit_count_q[0] == 0 && subframe_w[bit_count_q / 2] == 1'b1)`
200			`parity_count_q <= parity_count_q + 6'd1;`
201			`end`
202			`end`
203			`end`
204
205			`//-----------------------------------------------------------------`
206			`// Bit Counter`
207			`//-----------------------------------------------------------------`
208			`always @ (posedge rst_i or posedge clk_i)`
209			`begin`
210			`if (rst_i == 1'b1)`
211			`begin`
212			`bit_count_q <= 6'b0;`
213			`load_subframe_q <= 1'b1;`
214			`end`
215			`// Time to output a bit?`
216			`else if (bit_out_en_i)`
217			`begin`
218			`// 32 timeslots (x2 for double frequency)`
219			`if (bit_count_q == 6'd63)`
220			`begin`
221			`bit_count_q <= 6'd0;`
222			`load_subframe_q <= 1'b1;`
223			`end`
224			`else`
225			`begin`
226			`bit_count_q <= bit_count_q + 6'd1;`
227			`load_subframe_q <= 1'b0;`
228			`end`
229			`end`
230			`else`
231			`load_subframe_q <= 1'b0;`
232			`end`
233
234			`//-----------------------------------------------------------------`
235			`// Bit half toggle`
236			`//-----------------------------------------------------------------`
237			`always @ (posedge rst_i or posedge clk_i)`
238			`if (rst_i == 1'b1)`
239			`bit_toggle_q <= 1'b0;`
240			`// Time to output a bit?`
241			`else if (bit_out_en_i)`
242			`bit_toggle_q <= ~bit_toggle_q;`
243
244			`//-----------------------------------------------------------------`
245			`// Output bit (BMC encoded)`
246			`//-----------------------------------------------------------------`
247			`reg bit_r;`
248
249			`always @ *`
250			`begin`
251			`bit_r = spdif_out_q;`
252
253			`// Time to output a bit?`
254			`if (bit_out_en_i)`
255			`begin`
256			`// Preamble bits?`
257			`if (bit_count_q < 6'd8)`
258			`begin`
259			`bit_r = preamble_q[bit_count_q[2:0]];`
260			`end`
261			`// Normal timeslots`
262			`else if (bit_count_q < 6'd62)`
263			`begin`
264			`if (subframe_w[bit_count_q / 2] == 1'b0)`
265			`begin`
266			`if (bit_toggle_q == 1'b0)`
267			`bit_r = ~spdif_out_q;`
268			`else`
269			`bit_r = spdif_out_q;`
270			`end`
271			`else`
272			`bit_r = ~spdif_out_q;`
273			`end`
274			`// Parity timeslot`
275			`else`
276			`begin`
277			`// Even number of high bits, make odd`
278			`if (parity_count_q[0] == 1'b0)`
279			`begin`
280			`if (bit_toggle_q == 1'b0)`
281			`bit_r = ~spdif_out_q;`
282			`else`
283			`bit_r = spdif_out_q;`
284			`end`
285			`else`
286			`bit_r = ~spdif_out_q;`
287			`end`
288			`end`
289			`end`
290
291			`always @ (posedge rst_i or posedge clk_i )`
292			`if (rst_i == 1'b1)`
293			`spdif_out_q <= 1'b0;`
294			`else`
295			`spdif_out_q <= bit_r;`
296
297			`assign spdif_o = spdif_out_q;`
298
299			`endmodule`