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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [cordic.vhd] - Blame information for rev 4

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1 4 divadnauj
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.numeric_std.all;
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ENTITY cordic IS
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        PORT(
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                        iClk            :in             std_logic;
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                        iReset          :in     std_logic;
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                        istart          :in             std_logic;
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                        iEntrada        :in     std_logic_vector(31 downto 0);
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                        oSalida1        :out    std_logic_vector(31 downto 0);
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                        oSalida2        :out    std_logic_vector(31 downto 0);
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                        oready          :out    std_logic
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                );
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END cordic;
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ARCHITECTURE RTL OF cordic IS
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type estados is(s0,s1);
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signal ep,ns:estados;
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type memoria is array(0 to 19) of std_logic_vector(31 downto 0);
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constant        Angulo  : memoria :=(
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X"3F490FDB",
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X"3EED6338",
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X"3E7ADBB0",
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X"3DFEADD5",
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X"3D7FAADE",
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X"3CFFEAAE",
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X"3C7FFAAB",
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X"3BFFFEAB",
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X"3B7FFFAB",
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X"3AFFFFEB",
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X"3A7FFFFB",
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X"39FFFFFF",
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X"39800000",
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X"39000000",
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X"38800000",
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X"38000000",
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X"37800000",
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X"37000000",
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X"36800000",
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X"36000000");
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constant        Constante  : memoria :=(
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X"3F800000",
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X"3F000000",
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X"3E800000",
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X"3E000000",
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X"3D800000",
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X"3D000000",
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X"3C800000",
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X"3C000000",
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X"3B800000",
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X"3B000000",
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X"3A800000",
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X"3A000000",
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X"39800000",
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X"39000000",
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X"38800000",
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X"38000000",
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X"37800000",
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X"37000000",
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X"36800000",
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X"36000000");
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signal X,Y,Z :std_logic_vector(31 downto 0);
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signal xsub,yadd,zsub :std_logic_vector(31 downto 0);
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signal prodx,prody :std_logic_vector(31 downto 0);
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signal di2_i,diangulo :std_logic_vector(31 downto 0);
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signal counteri :std_logic_vector(4 downto 0);
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signal selx,enx,sely,eny,selz,enz,seli,eni :std_logic;
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signal w_case_cos: std_logic_vector(31 downto 0);
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signal w_case_sin: std_logic_vector(31 downto 0);
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signal w_case_en: std_logic;
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BEGIN
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FP_SUB_X: entity work.suma_resta
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        port map(operando1   =>unsigned(X),
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                        operando2        =>unsigned(prodx),
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                        operacion        =>"0010",
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                        std_logic_vector(resultado)      =>xsub);
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FP_ADD_Y: entity work.suma_resta
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        port map(operando1   =>unsigned(Y),
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                        operando2        =>unsigned(prody),
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                        operacion        =>"0001",
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                        std_logic_vector(resultado)      =>yadd);
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FP_SUB_Z: entity work.suma_resta
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        port map(operando1   =>unsigned(Z),
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                        operando2        =>unsigned(diangulo),
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                        operacion        =>"0010",
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                        std_logic_vector(resultado)      =>zsub);
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FP_MUL_X: entity work.multFP
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        port map(entrada_x  => Y,
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                         entrada_y      => di2_i,
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                         salida     => prodx);
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FP_MUL_Y: entity work.multFP
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        port map(entrada_x  => X,
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                         entrada_y      => di2_i,
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                         salida     => prody);
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di2_i <= (Constante(to_integer(unsigned(counteri)))(31) xor Z(31))&(Constante(to_integer(unsigned(counteri)))(30 downto 0));
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diangulo <= (Angulo(to_integer(unsigned(counteri)))(31) xor Z(31))&(Angulo(to_integer(unsigned(counteri)))(30 downto 0));
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Xreg:process(iClk,iReset)
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        begin
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                if iReset='0' then
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                        X <= (others=>'0');
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                elsif rising_edge(iClk) then
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                        if enx='1' then
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                                if selx='1' then
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                                        if w_case_en = '1' then
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                                                X <= w_case_cos;
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                                        else
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                                                if(unsigned(X(30 downto 23))=127 and unsigned(X(22 downto 0))=0) then
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                                                        X <= X"3f800000";
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                                                else
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                                                        X <= xsub;
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                                                end if;
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                                        end if;
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                                else
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                                        X <= X"3f1b74ee";
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                                end if;
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                        end if;
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                end if;
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        end process Xreg;
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Yreg:process(iClk,iReset)
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        begin
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                if iReset='0' then
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                        Y <= (others=>'0');
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                elsif rising_edge(iClk) then
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                        if eny='1' then
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                                if sely='1' then
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                                        if w_case_en = '1' then
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                                                Y <= w_case_sin;
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                                        else
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                                                if(unsigned(Y(30 downto 23))=127 and unsigned(Y(22 downto 0))=0) then
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                                                        Y <= X"3f800000";
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                                                else
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                                                        Y <= yadd;
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                                                end if;
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                                        end if;
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                                else
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                                        Y <= (others=>'0');
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                                end if;
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                        end if;
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                end if;
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        end process Yreg;
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Zreg:process(iClk,iReset)
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        begin
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                if iReset='0' then
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                        Z <= (others=>'0');
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                elsif rising_edge(iClk) then
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                        if enz='1' then
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                                if selz='1' then
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                                        Z <= zsub;
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                                else
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                                        Z <= iEntrada;
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                                end if;
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                        end if;
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                end if;
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        end process Zreg;
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ireg:process(iClk,iReset)
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        begin
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                if iReset='0' then
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                        counteri <= (others=>'0');
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                elsif rising_edge(iClk) then
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                        if eni='1' then
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                                if seli='1' then
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                                        counteri <= std_logic_vector(unsigned(counteri)+1);
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                                else
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                                        counteri <= (others=>'0');
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                                end if;
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                        end if;
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                end if;
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        end process ireg;
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FSM_NS:process(istart,ep,counteri,w_case_en)
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        begin
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                case ep is
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                        when s0 =>
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                                if istart='1' then
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                                        ns <= s1;
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                                else
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                                        ns <= s0;
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                                end if;
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                        when s1 =>
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                                if unsigned(counteri)=16 or w_case_en='1' then
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                                        ns <= s0;
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                                else
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                                        ns <= s1;
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                                end if;
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                        when others=>
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                end case;
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        end process;
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FSM_TS:process(iClk,iReset)
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        begin
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                if iReset='0' then
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                        ep <= s0;
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                elsif rising_edge(iClk) then
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                        ep <= ns;
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                end if;
220
        end process;
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FSM_OUT:process(istart,ep,counteri,w_case_en)
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        begin
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                case ep is
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                        when s0 =>
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                                oready <= '1';
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                                if istart='1' then
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                                        enx   <= '1';
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                                        selx  <= '0';
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                                        eny   <= '1';
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                                        sely  <= '0';
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                                        enz   <= '1';
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                                        selz  <= '0';
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                                        eni   <= '1';
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                                        seli  <= '0';
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                                else
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                                        enx   <= '0';
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                                        selx  <= '0';
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                                        eny   <= '0';
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                                        sely  <= '0';
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                                        enz   <= '0';
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                                        selz  <= '0';
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                                        eni   <= '0';
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                                        seli  <= '0';
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                                end if;
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                        when s1 =>
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                                oready <= '0';
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                                enx   <= '1';
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                                selx  <= '1';
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                                eny   <= '1';
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                                sely  <= '1';
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                                enz   <= '1';
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                                selz  <= '1';
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                                if unsigned(counteri)=16 or w_case_en='1' then
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                                        eni   <= '0';
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                                        seli  <= '0';
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                                else
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                                        eni   <= '1';
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                                        seli  <= '1';
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                                end if;
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                        when others=>
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                                oready <= '0';
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                                enx   <= '0';
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                                selx  <= '0';
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                                eny   <= '0';
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                                sely  <= '0';
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                                enz   <= '0';
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                                selz  <= '0';
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                                eni   <= '0';
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                                seli  <= '0';
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                end case;
272
        end process;
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        IEEECASE: entity work.cordic_ieee
276
                port map(
277
                i_reset                 => iReset,
278
                i_clk                   => iClk,
279
                i_data                  => iEntrada,
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                i_en                    => enx,
281
                i_sel                   => selx,
282
                o_case_cos              => w_case_cos,
283
                o_case_sin              => w_case_sin,
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                o_case_en               => w_case_en
285
                );
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287
 
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--      ieeeprocess: process(w_case_en)
289
 
290
--      begin
291
 
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--              case w_case_en is
293
--              when '0'        => oSalida1 <= X;                       oSalida2 <= Y;
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--              when '1'        => oSalida1 <= w_case_cos;      oSalida2 <= w_case_sin;
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--              when others => oSalida1 <= X;                   oSalida2 <= Y;
296
--              end case;
297
 
298
--      end process;
299
 
300
        oSalida1 <= X;
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        oSalida2 <= Y;
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END RTL;

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