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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.numeric_std.all;
 
ENTITY cordic IS
        PORT(
                        iClk            :in             std_logic;
                        iReset          :in     std_logic;
                        istart          :in             std_logic;
                        iEntrada        :in     std_logic_vector(31 downto 0);
                        oSalida1        :out    std_logic_vector(31 downto 0);
                        oSalida2        :out    std_logic_vector(31 downto 0);
                        oready          :out    std_logic
                );
END cordic;
 
ARCHITECTURE RTL OF cordic IS
type estados is(s0,s1);
signal ep,ns:estados;
 
type memoria is array(0 to 19) of std_logic_vector(31 downto 0);
 
constant        Angulo  : memoria :=(
X"3F490FDB",
X"3EED6338",
X"3E7ADBB0",
X"3DFEADD5",
X"3D7FAADE",
X"3CFFEAAE",
X"3C7FFAAB",
X"3BFFFEAB",
X"3B7FFFAB",
X"3AFFFFEB",
X"3A7FFFFB",
X"39FFFFFF",
X"39800000",
X"39000000",
X"38800000",
X"38000000",
X"37800000",
X"37000000",
X"36800000",
X"36000000");
 
constant        Constante  : memoria :=(
X"3F800000",
X"3F000000",
X"3E800000",
X"3E000000",
X"3D800000",
X"3D000000",
X"3C800000",
X"3C000000",
X"3B800000",
X"3B000000",
X"3A800000",
X"3A000000",
X"39800000",
X"39000000",
X"38800000",
X"38000000",
X"37800000",
X"37000000",
X"36800000",
X"36000000");
 
signal X,Y,Z :std_logic_vector(31 downto 0);
signal xsub,yadd,zsub :std_logic_vector(31 downto 0);
signal prodx,prody :std_logic_vector(31 downto 0);
signal di2_i,diangulo :std_logic_vector(31 downto 0);
signal counteri :std_logic_vector(4 downto 0);
signal selx,enx,sely,eny,selz,enz,seli,eni :std_logic;
 
signal w_case_cos: std_logic_vector(31 downto 0);
signal w_case_sin: std_logic_vector(31 downto 0);
signal w_case_en: std_logic;
 
 
 
BEGIN
 
FP_SUB_X: entity work.suma_resta
        port map(operando1   =>unsigned(X),
                        operando2        =>unsigned(prodx),
                        operacion        =>"0010",
                        std_logic_vector(resultado)      =>xsub);
 
 
FP_ADD_Y: entity work.suma_resta
        port map(operando1   =>unsigned(Y),
                        operando2        =>unsigned(prody),
                        operacion        =>"0001",
                        std_logic_vector(resultado)      =>yadd);
 
FP_SUB_Z: entity work.suma_resta
        port map(operando1   =>unsigned(Z),
                        operando2        =>unsigned(diangulo),
                        operacion        =>"0010",
                        std_logic_vector(resultado)      =>zsub);
 
FP_MUL_X: entity work.multFP
        port map(entrada_x  => Y,
                         entrada_y      => di2_i,
                         salida     => prodx);
 
FP_MUL_Y: entity work.multFP
        port map(entrada_x  => X,
                         entrada_y      => di2_i,
                         salida     => prody);
 
 
di2_i <= (Constante(to_integer(unsigned(counteri)))(31) xor Z(31))&(Constante(to_integer(unsigned(counteri)))(30 downto 0));
diangulo <= (Angulo(to_integer(unsigned(counteri)))(31) xor Z(31))&(Angulo(to_integer(unsigned(counteri)))(30 downto 0));
 
 
Xreg:process(iClk,iReset)
        begin
                if iReset='0' then
                        X <= (others=>'0');
                elsif rising_edge(iClk) then
                        if enx='1' then
                                if selx='1' then
                                        if w_case_en = '1' then
                                                X <= w_case_cos;
                                        else
                                                if(unsigned(X(30 downto 23))=127 and unsigned(X(22 downto 0))=0) then
                                                        X <= X"3f800000";
                                                else
                                                        X <= xsub;
                                                end if;
                                        end if;
                                else
                                        X <= X"3f1b74ee";
                                end if;
                        end if;
                end if;
        end process Xreg;
 
Yreg:process(iClk,iReset)
        begin
                if iReset='0' then
                        Y <= (others=>'0');
                elsif rising_edge(iClk) then
                        if eny='1' then
                                if sely='1' then
                                        if w_case_en = '1' then
                                                Y <= w_case_sin;
                                        else
                                                if(unsigned(Y(30 downto 23))=127 and unsigned(Y(22 downto 0))=0) then
                                                        Y <= X"3f800000";
                                                else
                                                        Y <= yadd;
                                                end if;
                                        end if;
                                else
                                        Y <= (others=>'0');
                                end if;
                        end if;
                end if;
        end process Yreg;
 
 
Zreg:process(iClk,iReset)
        begin
                if iReset='0' then
                        Z <= (others=>'0');
                elsif rising_edge(iClk) then
                        if enz='1' then
                                if selz='1' then
                                        Z <= zsub;
                                else
                                        Z <= iEntrada;
                                end if;
                        end if;
                end if;
        end process Zreg;
 
ireg:process(iClk,iReset)
        begin
                if iReset='0' then
                        counteri <= (others=>'0');
                elsif rising_edge(iClk) then
                        if eni='1' then
                                if seli='1' then
                                        counteri <= std_logic_vector(unsigned(counteri)+1);
                                else
                                        counteri <= (others=>'0');
                                end if;
                        end if;
                end if;
        end process ireg;
 
FSM_NS:process(istart,ep,counteri,w_case_en)
        begin
                case ep is
                        when s0 =>
                                if istart='1' then
                                        ns <= s1;
                                else
                                        ns <= s0;
                                end if;
                        when s1 =>
                                if unsigned(counteri)=16 or w_case_en='1' then
                                        ns <= s0;
                                else
                                        ns <= s1;
                                end if;
                        when others=>
                end case;
        end process;
 
 
FSM_TS:process(iClk,iReset)
        begin
                if iReset='0' then
                        ep <= s0;
                elsif rising_edge(iClk) then
                        ep <= ns;
                end if;
        end process;
 
FSM_OUT:process(istart,ep,counteri,w_case_en)
        begin
                case ep is
                        when s0 =>
                                oready <= '1';
                                if istart='1' then
                                        enx   <= '1';
                                        selx  <= '0';
                                        eny   <= '1';
                                        sely  <= '0';
                                        enz   <= '1';
                                        selz  <= '0';
                                        eni   <= '1';
                                        seli  <= '0';
                                else
                                        enx   <= '0';
                                        selx  <= '0';
                                        eny   <= '0';
                                        sely  <= '0';
                                        enz   <= '0';
                                        selz  <= '0';
                                        eni   <= '0';
                                        seli  <= '0';
                                end if;
                        when s1 =>
                                oready <= '0';
                                enx   <= '1';
                                selx  <= '1';
                                eny   <= '1';
                                sely  <= '1';
                                enz   <= '1';
                                selz  <= '1';
                                if unsigned(counteri)=16 or w_case_en='1' then
                                        eni   <= '0';
                                        seli  <= '0';
                                else
                                        eni   <= '1';
                                        seli  <= '1';
                                end if;
                        when others=>
                                oready <= '0';
                                enx   <= '0';
                                selx  <= '0';
                                eny   <= '0';
                                sely  <= '0';
                                enz   <= '0';
                                selz  <= '0';
                                eni   <= '0';
                                seli  <= '0';
                end case;
        end process;
 
 
        IEEECASE: entity work.cordic_ieee
                port map(
                i_reset                 => iReset,
                i_clk                   => iClk,
                i_data                  => iEntrada,
                i_en                    => enx,
                i_sel                   => selx,
                o_case_cos              => w_case_cos,
                o_case_sin              => w_case_sin,
                o_case_en               => w_case_en
                );
 
 
--      ieeeprocess: process(w_case_en)
 
--      begin
 
--              case w_case_en is
--              when '0'        => oSalida1 <= X;                       oSalida2 <= Y;
--              when '1'        => oSalida1 <= w_case_cos;      oSalida2 <= w_case_sin;
--              when others => oSalida1 <= X;                   oSalida2 <= Y;
--              end case;
 
--      end process;
 
        oSalida1 <= X;
        oSalida2 <= Y;
 
END RTL;

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Subversion Repositories special_functions_unit

[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [cordic.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	4	divadnauj	`LIBRARY IEEE;`
2			`USE IEEE.STD_LOGIC_1164.ALL;`
3			`USE IEEE.numeric_std.all;`
4
5			`ENTITY cordic IS`
6			`PORT(`
7			`iClk :in std_logic;`
8			`iReset :in std_logic;`
9			`istart :in std_logic;`
10			`iEntrada :in std_logic_vector(31 downto 0);`
11			`oSalida1 :out std_logic_vector(31 downto 0);`
12			`oSalida2 :out std_logic_vector(31 downto 0);`
13			`oready :out std_logic`
14			`);`
15			`END cordic;`
16
17			`ARCHITECTURE RTL OF cordic IS`
18			`type estados is(s0,s1);`
19			`signal ep,ns:estados;`
20
21			`type memoria is array(0 to 19) of std_logic_vector(31 downto 0);`
22
23			`constant Angulo : memoria :=(`
24			`X"3F490FDB",`
25			`X"3EED6338",`
26			`X"3E7ADBB0",`
27			`X"3DFEADD5",`
28			`X"3D7FAADE",`
29			`X"3CFFEAAE",`
30			`X"3C7FFAAB",`
31			`X"3BFFFEAB",`
32			`X"3B7FFFAB",`
33			`X"3AFFFFEB",`
34			`X"3A7FFFFB",`
35			`X"39FFFFFF",`
36			`X"39800000",`
37			`X"39000000",`
38			`X"38800000",`
39			`X"38000000",`
40			`X"37800000",`
41			`X"37000000",`
42			`X"36800000",`
43			`X"36000000");`
44
45			`constant Constante : memoria :=(`
46			`X"3F800000",`
47			`X"3F000000",`
48			`X"3E800000",`
49			`X"3E000000",`
50			`X"3D800000",`
51			`X"3D000000",`
52			`X"3C800000",`
53			`X"3C000000",`
54			`X"3B800000",`
55			`X"3B000000",`
56			`X"3A800000",`
57			`X"3A000000",`
58			`X"39800000",`
59			`X"39000000",`
60			`X"38800000",`
61			`X"38000000",`
62			`X"37800000",`
63			`X"37000000",`
64			`X"36800000",`
65			`X"36000000");`
66
67			`signal X,Y,Z :std_logic_vector(31 downto 0);`
68			`signal xsub,yadd,zsub :std_logic_vector(31 downto 0);`
69			`signal prodx,prody :std_logic_vector(31 downto 0);`
70			`signal di2_i,diangulo :std_logic_vector(31 downto 0);`
71			`signal counteri :std_logic_vector(4 downto 0);`
72			`signal selx,enx,sely,eny,selz,enz,seli,eni :std_logic;`
73
74			`signal w_case_cos: std_logic_vector(31 downto 0);`
75			`signal w_case_sin: std_logic_vector(31 downto 0);`
76			`signal w_case_en: std_logic;`
77
78
79
80			`BEGIN`
81
82			`FP_SUB_X: entity work.suma_resta`
83			`port map(operando1 =>unsigned(X),`
84			`operando2 =>unsigned(prodx),`
85			`operacion =>"0010",`
86			`std_logic_vector(resultado) =>xsub);`
87
88
89			`FP_ADD_Y: entity work.suma_resta`
90			`port map(operando1 =>unsigned(Y),`
91			`operando2 =>unsigned(prody),`
92			`operacion =>"0001",`
93			`std_logic_vector(resultado) =>yadd);`
94
95			`FP_SUB_Z: entity work.suma_resta`
96			`port map(operando1 =>unsigned(Z),`
97			`operando2 =>unsigned(diangulo),`
98			`operacion =>"0010",`
99			`std_logic_vector(resultado) =>zsub);`
100
101			`FP_MUL_X: entity work.multFP`
102			`port map(entrada_x => Y,`
103			`entrada_y => di2_i,`
104			`salida => prodx);`
105
106			`FP_MUL_Y: entity work.multFP`
107			`port map(entrada_x => X,`
108			`entrada_y => di2_i,`
109			`salida => prody);`
110
111
112			`di2_i <= (Constante(to_integer(unsigned(counteri)))(31) xor Z(31))&(Constante(to_integer(unsigned(counteri)))(30 downto 0));`
113			`diangulo <= (Angulo(to_integer(unsigned(counteri)))(31) xor Z(31))&(Angulo(to_integer(unsigned(counteri)))(30 downto 0));`
114
115
116			`Xreg:process(iClk,iReset)`
117			`begin`
118			`if iReset='0' then`
119			`X <= (others=>'0');`
120			`elsif rising_edge(iClk) then`
121			`if enx='1' then`
122			`if selx='1' then`
123			`if w_case_en = '1' then`
124			`X <= w_case_cos;`
125			`else`
126			`if(unsigned(X(30 downto 23))=127 and unsigned(X(22 downto 0))=0) then`
127			`X <= X"3f800000";`
128			`else`
129			`X <= xsub;`
130			`end if;`
131			`end if;`
132			`else`
133			`X <= X"3f1b74ee";`
134			`end if;`
135			`end if;`
136			`end if;`
137			`end process Xreg;`
138
139			`Yreg:process(iClk,iReset)`
140			`begin`
141			`if iReset='0' then`
142			`Y <= (others=>'0');`
143			`elsif rising_edge(iClk) then`
144			`if eny='1' then`
145			`if sely='1' then`
146			`if w_case_en = '1' then`
147			`Y <= w_case_sin;`
148			`else`
149			`if(unsigned(Y(30 downto 23))=127 and unsigned(Y(22 downto 0))=0) then`
150			`Y <= X"3f800000";`
151			`else`
152			`Y <= yadd;`
153			`end if;`
154			`end if;`
155			`else`
156			`Y <= (others=>'0');`
157			`end if;`
158			`end if;`
159			`end if;`
160			`end process Yreg;`
161
162
163			`Zreg:process(iClk,iReset)`
164			`begin`
165			`if iReset='0' then`
166			`Z <= (others=>'0');`
167			`elsif rising_edge(iClk) then`
168			`if enz='1' then`
169			`if selz='1' then`
170			`Z <= zsub;`
171			`else`
172			`Z <= iEntrada;`
173			`end if;`
174			`end if;`
175			`end if;`
176			`end process Zreg;`
177
178			`ireg:process(iClk,iReset)`
179			`begin`
180			`if iReset='0' then`
181			`counteri <= (others=>'0');`
182			`elsif rising_edge(iClk) then`
183			`if eni='1' then`
184			`if seli='1' then`
185			`counteri <= std_logic_vector(unsigned(counteri)+1);`
186			`else`
187			`counteri <= (others=>'0');`
188			`end if;`
189			`end if;`
190			`end if;`
191			`end process ireg;`
192
193			`FSM_NS:process(istart,ep,counteri,w_case_en)`
194			`begin`
195			`case ep is`
196			`when s0 =>`
197			`if istart='1' then`
198			`ns <= s1;`
199			`else`
200			`ns <= s0;`
201			`end if;`
202			`when s1 =>`
203			`if unsigned(counteri)=16 or w_case_en='1' then`
204			`ns <= s0;`
205			`else`
206			`ns <= s1;`
207			`end if;`
208			`when others=>`
209			`end case;`
210			`end process;`
211
212
213			`FSM_TS:process(iClk,iReset)`
214			`begin`
215			`if iReset='0' then`
216			`ep <= s0;`
217			`elsif rising_edge(iClk) then`
218			`ep <= ns;`
219			`end if;`
220			`end process;`
221
222			`FSM_OUT:process(istart,ep,counteri,w_case_en)`
223			`begin`
224			`case ep is`
225			`when s0 =>`
226			`oready <= '1';`
227			`if istart='1' then`
228			`enx <= '1';`
229			`selx <= '0';`
230			`eny <= '1';`
231			`sely <= '0';`
232			`enz <= '1';`
233			`selz <= '0';`
234			`eni <= '1';`
235			`seli <= '0';`
236			`else`
237			`enx <= '0';`
238			`selx <= '0';`
239			`eny <= '0';`
240			`sely <= '0';`
241			`enz <= '0';`
242			`selz <= '0';`
243			`eni <= '0';`
244			`seli <= '0';`
245			`end if;`
246			`when s1 =>`
247			`oready <= '0';`
248			`enx <= '1';`
249			`selx <= '1';`
250			`eny <= '1';`
251			`sely <= '1';`
252			`enz <= '1';`
253			`selz <= '1';`
254			`if unsigned(counteri)=16 or w_case_en='1' then`
255			`eni <= '0';`
256			`seli <= '0';`
257			`else`
258			`eni <= '1';`
259			`seli <= '1';`
260			`end if;`
261			`when others=>`
262			`oready <= '0';`
263			`enx <= '0';`
264			`selx <= '0';`
265			`eny <= '0';`
266			`sely <= '0';`
267			`enz <= '0';`
268			`selz <= '0';`
269			`eni <= '0';`
270			`seli <= '0';`
271			`end case;`
272			`end process;`
273
274
275			`IEEECASE: entity work.cordic_ieee`
276			`port map(`
277			`i_reset => iReset,`
278			`i_clk => iClk,`
279			`i_data => iEntrada,`
280			`i_en => enx,`
281			`i_sel => selx,`
282			`o_case_cos => w_case_cos,`
283			`o_case_sin => w_case_sin,`
284			`o_case_en => w_case_en`
285			`);`
286
287
288			`-- ieeeprocess: process(w_case_en)`
289
290			`-- begin`
291
292			`-- case w_case_en is`
293			`-- when '0' => oSalida1 <= X; oSalida2 <= Y;`
294			`-- when '1' => oSalida1 <= w_case_cos; oSalida2 <= w_case_sin;`
295			`-- when others => oSalida1 <= X; oSalida2 <= Y;`
296			`-- end case;`
297
298			`-- end process;`
299
300			`oSalida1 <= X;`
301			`oSalida2 <= Y;`
302
303			`END RTL;`