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[/] [special_functions_unit/] [Open_source_SFU/] [cordic_vhdl/] [parts/] [suma_resta.vhd] - Blame information for rev 4

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1 4 divadnauj
 
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-- operacion de suma y resta en flotante.
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Library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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--use IEEE.numeric_bit.all;
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--use IEEE.STD_LOGIC_ARITH.ALL;
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entity suma_resta is
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generic(
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                long : natural := 32
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                );
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port(
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        operando1, operando2: in unsigned(long-1 downto 0);
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        operacion: in unsigned(3 downto 0);
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        resultado: out unsigned(long-1 downto 0)
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        );
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end suma_resta;
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architecture ar of suma_resta is
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                component prueba is
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                Port ( FP_A : in  std_logic_vector (31 downto 0);
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                        FP_B : in  std_logic_vector (31 downto 0);
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                        add_sub: in std_logic;
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                        FP_Z : out  std_logic_vector (31 downto 0));
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        end component;
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begin
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        P2: prueba port map(
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                                FP_A =>STD_LOGIC_VECTOR(operando1),
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                                FP_B =>STD_LOGIC_VECTOR(operando2),
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                                add_sub =>operacion(0),
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                                unsigned(FP_Z) =>resultado
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                                );
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end ar;
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