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[/] [special_functions_unit/] [Open_source_SFU/] [log2_vhdl/] [parts/] [CLZ.vhd] - Blame information for rev 4

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1 4 divadnauj
--*************************************************************************--
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-- Count Leading Zero/Ones
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--*************************************************************************--
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-- Universidad Pedagogica y Tecnologica de Colombia.
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-- Facultad de ingenieria.
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-- Escuela de ingenieria Electronica - extension Tunja.
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-- 
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-- Autor: Cristhian Fernando Moreno Manrique
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-- Marzo 2020
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--*************************************************************************--
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--
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--      MODE            0: Count Leading Zeros
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--                              1: Count Leading Ones
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--
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--      DATA_BITS       only 2^x data bits: 2, 4, 8, ..., 128... 
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--
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--
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--      o_MSB_zeros is activated when i_data is only 0's or only 1's for Count
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--      Leading Zeros and Count Leading One's modes respectively.
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-----------------------------------------------------------------------------   
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library ieee;
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        use ieee.std_logic_1164.all;
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        use ieee.numeric_std.all;
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        use work.log2_pkg.all;
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entity CLZ is
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        generic (MODE                   :               std_logic:= '0';
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                                DATA_BITS       :               integer := 32);
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        port      (i_data               : in    std_logic_vector(DATA_BITS-1 downto 0);
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                                o_zeros         : out std_logic_vector(f_log2(DATA_BITS)-1 downto 0);
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                                o_MSB_zeros     : out std_logic);
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end CLZ;
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-----------------------------------------------------------------------------   
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architecture Behavioral of CLZ is
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        signal s_data: std_logic_vector(i_data'left downto 0);
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        signal s_zeros: std_logic_vector(o_zeros'left downto 0);
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        type array_or is array (o_zeros'left downto 0) of std_logic_vector(i_data'left downto 0);
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        signal w_or: array_or;
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        -- w_and se utiliza para calcular o_MSB_zeros
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        signal w_and                    : std_logic_vector(o_zeros'left downto 0);
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        signal w_LSB_data               : std_logic;
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        signal w_MSB_zeros      : std_logic;
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begin
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        -- MODE CONFIG ------------------------------------------------------------     
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        MD0: if MODE = '0' generate
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                s_data <= i_data;
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        end generate MD0;
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        MD1: if MODE = '1' generate
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                s_data <= not(i_data);
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        end generate MD1;
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        -- calculate o_zeros ------------------------------------------------------     
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        w_or(o_zeros'left) <= '0' & s_data(s_data'left downto 1);
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        U: for i in o_zeros'left downto 1 generate
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                signal aux: std_logic_vector(2**(i+1)-1 downto 0);
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        begin
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                aux(0) <= not(w_or(i)(0));
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                UU: for ii in 1 to (2**(i+1)-2) generate
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                         UU_impar:if ((ii+1) mod 2) = 0 generate
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                                w_or(i-1)((ii+1)/2-1) <= w_or(i)(ii+1) or w_or(i)(ii);
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                                aux(ii)<= w_or(i)(ii) or aux(ii-1);
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                         end generate;
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                         UU_par:if (ii mod 2) = 0 generate
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                                aux(ii)<= not(w_or(i)(ii)) and aux(ii-1);
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                         end generate;
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                end generate UU;
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                s_zeros((s_zeros'left)-i) <= aux(aux'left-1);
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        end generate U;
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        s_zeros(s_zeros'left) <= not(w_or(0)(0));
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        --- calculate o_MSB_zeros -------------------------------------------------
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        w_and(0) <= s_zeros(0);
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        M: for i in 1 to s_zeros'left generate
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                w_and(i) <= w_and(i-1) and s_zeros(i);
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                o_zeros(i)      <= s_zeros(i) and not(w_MSB_zeros);
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        end generate M;
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        w_LSB_data      <= s_data(0);
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        w_MSB_zeros     <= not(w_LSB_data) and w_and(w_and'left);
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        -- result ------------------------------------------------------------------
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        o_zeros(0) <= s_zeros(0) and not(w_MSB_zeros);
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        o_MSB_zeros <=  w_MSB_zeros;
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end Behavioral;

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