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-- Nombre de archivo    : sum_ripple_carry_adder.vhd
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--      Titulo                          : Sumador/restador punto fijo
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-----------------------------------------------------------------------------   
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-- Descripcion                  : Sumador/restador arquitectura Ripple Carry Adder.
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--                                                        Permite aplicar complemento 1 a uno o ambos numeros
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--                                                        de entrada.
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--
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--      WIDE                            : numero de bits de los numeros a operar
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--              C1                                      : 3 -> complemento 1 a ambos numeros
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--                                                        2 -> complemento 1 a numero 2
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--                                                        1 -> complemento 1 a numero 1
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--                                                        0 -> no aplicar C1
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--
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--      i_term1                 : Numero 1
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--      i_term2                 : Numero 2
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--    i_cin                             : acarreo de entrada
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--      o_result                        : Resultado
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--    o_cout                    : Acarreo de salida
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--
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-----------------------------------------------------------------------------   
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-- Universidad Pedagogica y Tecnologica de Colombia.
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-- Facultad de ingenieria.
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-- Escuela de ingenieria Electronica - extension Tunja.
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-- 
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-- Autor: Cristhian Fernando Moreno Manrique
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-- Marzo 2020
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-----------------------------------------------------------------------------   
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library ieee;
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        use ieee.std_logic_1164.all;
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entity sum_ripple_carry_adder is
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        generic (WIDE           :               natural:= 32;
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                                C1                      :               natural:= 0);                                                            -- sin complemento 1 por defecto
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        port      (i_term1      : in    std_logic_vector(WIDE-1 downto 0);
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                                i_term2 : in    std_logic_vector(WIDE-1 downto 0);
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                                i_cin           : in    std_logic;
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                                o_sum           : out   std_logic_vector(WIDE-1 downto 0);
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                                o_cout  : out std_logic);
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end entity;
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-----------------------------------------------------------------------------                           
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architecture main of sum_ripple_carry_adder is
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        signal w_cout           :               std_logic_vector(WIDE-1 downto 0);
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        signal w_term1          :               std_logic_vector(WIDE-1 downto 0);
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        signal w_term2          :               std_logic_vector(WIDE-1 downto 0);
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begin
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        assert C1 > 3
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                report "Opcion de C1 no disponible, intente con 0, 1, 2 o 3"
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                severity note;
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        BLOCK_A:
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        for i in WIDE-1 downto 0 generate
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                -----------------------------------------------------------------------
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                -- configuracion de complemento a uno
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                -----------------------------------------------------------------------
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                MD0: if C1 = 0 generate
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                        w_term1(i) <= i_term1(i);
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                        w_term2(i) <= i_term2(i);
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                end generate MD0;
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                MD1: if C1 = 1 generate
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                        w_term1(i) <= not(i_term1(i));
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                        w_term2(i) <= i_term2(i);
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                end generate MD1;
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                MD2: if C1 = 2 generate
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                        w_term1(i) <= i_term1(i);
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                        w_term2(i) <= not(i_term2(i));
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                end generate MD2;
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                MD3: if C1 = 3 generate
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                        w_term1(i) <= not(i_term1(i));
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                        w_term2(i) <= not(i_term2(i));
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                end generate MD3;
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                -----------------------------------------------------------------------
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                -- arquitectura Ripple Carry Adder
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                -----------------------------------------------------------------------         
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                LowBit: if i=0 generate
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                        a: entity work.FA port map(
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                                i_term1 => w_term1(i),
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                                i_term2 => w_term2(i),
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                                i_cin           => i_cin,
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                                o_Sum   => o_sum(i),
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                                o_cout  => w_cout(i)
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                        );
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                end generate;
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                OtherBits: if i/=0 generate
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                        b: entity work.FA port map(
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                                i_term1 => w_term1(i),
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                                i_term2 => w_term2(i),
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                                i_cin   => w_cout(i-1),
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                                o_sum   => o_sum(i),
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                                o_cout  => w_cout(i)
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                        );
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                end generate;
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        end generate BLOCK_A;
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        o_cout <= w_cout(WIDE-1);
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end main;
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