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[/] [special_functions_unit/] [Open_source_SFU/] [rsqrt_vhdl/] [rsqrt.vhd] - Blame information for rev 4

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1 4 divadnauj
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.log2_pkg.all;
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entity rsqrt is
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port(
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        i_x             :in     std_logic_vector(31 downto 0);
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        o_rsqrt :out std_logic_vector(31 downto 0)
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);
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end entity rsqrt;
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architecture oper of rsqrt is
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constant K      :unsigned(31 downto 0) := X"5F375A86"; --X"5F3759DF";
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signal Y        :std_logic_vector(31 downto 0);
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signal X2       :std_logic_vector(31 downto 0);
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signal mult1, mult2, mult3, mult4, resta :std_logic_vector(31 downto 0);
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signal w_case_en        : std_logic;
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signal w_ieeecase       : std_logic_vector(i_x'left downto 0);
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begin
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Y <= std_logic_vector(K-unsigned('0'&i_x(31 downto 1)));
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X2 <= i_x(31)&std_logic_vector(unsigned(i_x(30 downto 23))-1)&i_x(22 downto 0);
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FP1: entity work.multFP
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        port map(
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        entrada_x  => X"3fc00000",
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        entrada_y  => Y,
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        salida     => mult1
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        );
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FP2: entity work.multFP
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        port map(
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        entrada_x  => Y,
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        entrada_y  => Y,
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        salida     => mult2
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        );
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FP3: entity work.multFP
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        port map(
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        entrada_x  => Y,
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        entrada_y  => X2,
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        salida     => mult3
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        );
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FP4: entity work.multFP
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        port map(
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        entrada_x  => mult2,
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        entrada_y  => mult3,
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        salida     => mult4
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        );
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SUB: entity work.suma_resta
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        port map(
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        operando1  => unsigned(mult1),
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        operando2  => unsigned(mult4),
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        operacion  => "0010",
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        std_logic_vector(resultado)  => resta
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        );
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IEEECASE: entity work.rsqrt_ieee
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        port map(
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        i_data          => i_x,
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        o_case          => w_ieeecase,
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        o_case_en       => w_case_en
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        );
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with w_case_en select
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        o_rsqrt <=  resta               when '0',
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                                w_ieeecase      when '1',
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                                resta           when others;
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end oper;

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