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[/] [spi2ram/] [trunk/] [tb2.v] - Blame information for rev 5

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module top_module ();
        reg clk=0;
 
    reg spi_sck,spi_cs,spi_mosi,spi_clk ;
 
    wire spi_miso;
    wire[16:0] nvram_addr;
    wire nvram_en;
    wire nvram_g;
    wire nvram_w;
 
    reg sys_clk;
    reg sys_rstn;
    reg [7:0] rDin;
 
    parameter           clockperiod = 10;
    parameter           clockperiod1 = 8;
 
    initial
    begin
        rDin = 0;
        sys_rstn = 0;
        sys_clk = 0;
        #15
        sys_rstn = 1;
    end
 
    initial
    begin
        spi_sck = 1'b0;
        //repeat(1000) spi_sck = #(clockperiod/2)~spi_sck;
    end
 
 
        initial `probe_start;   // Start the timing diagram
 
        // A testbench
 
        initial begin
     #80;
         spi_cs = 1'b0;
         #20;spi_cs = 1'b1;
     #20;spi_cs = 1'b0;
        datasend(8'h03);
        datasend(8'h01);
        datasend(8'h55);
        rDin = 8'h11;
        datasend(8'ha1);
        rDin = 8'h33;
        datasend(8'hdd);
        rDin = 8'h22;
        datasend(8'h11);
        rDin = 8'h77;
        datasend(8'h22);
        rDin = 8'h99;
        datasend(8'h44);
 
         spi_cs = 1'b1;
         #20;
 
         $finish;            // Quit the simulation
        end
 
 
 
    task datasend(input [7:0] senddata);
        begin
        #5; spi_sck = 1'b0;
            spi_mosi = senddata[7];
        #5; spi_sck = 1'b1;
        #5; spi_sck = 1'b0;
            spi_mosi = senddata[6];
        #5;  spi_sck = 1'b1;
        #5;  spi_sck = 1'b0;
            spi_mosi = senddata[5];
        #5; spi_sck = 1'b1;
        #5;  spi_sck = 1'b0;
            spi_mosi = senddata[4];
        #5; spi_sck = 1'b1;
        #5; spi_sck = 1'b0;
            spi_mosi = senddata[3];
        #5; spi_sck = 1'b1;
        #5; spi_sck = 1'b0;
            spi_mosi = senddata[2];
        #5; spi_sck = 1'b1;
        #5; spi_sck = 1'b0;
            spi_mosi = senddata[1];
        #5; spi_sck = 1'b1;
        #5;  spi_sck = 1'b0;
            spi_mosi = senddata[0];
        #5; spi_sck = 1'b1;
        #5; spi_sck = 1'b0;
        #5;
 
        end
    endtask
    spi_slave_nvram spi_slave_nvram_sim (
 
    .spi_sck(spi_sck),
    .spi_cs(spi_cs),
    .spi_mosi(spi_mosi),
        .spi_miso(spi_miso),
 
        .sAddress(sAddress) ,
        .sCSn(sCSn),
        .sOEn(sOEn),
        .sWRn(sWRn),
        .sDqDir(sDqDir),
        .sDqOut(sDqOut),
        .sDqIn(rDin)
    );
 
    `probe(spi_sck);        // Probe signal "clk"
    `probe(spi_mosi);        // Probe signal "clk" 
        `probe(sys_rstn);        // Probe signal "clk"
        `probe(spi_cs);        // Probe signal "clk"
    `probe(spi_miso);        // Probe signal "clk" 
endmodule
 
module spi_slave_nvram
(
    //spi interface
    input spi_sck,
    input spi_cs,
    input spi_mosi,
    output spi_miso,
    //nvram interface  
 
    output [16:0] sAddress ,
    output sCSn,
    output sOEn,
    output sWRn,
    output sDqDir,
    output [7:0] sDqOut,
    input [7:0] sDqIn
);
 
    reg [7:0] rINBUF;
    reg [7:0] rOUTBUF;
    assign spi_miso = rOUTBUF[7];
 
 
    reg [5:0] rCnt;
    reg  rCntOV;
    wire sCnt8;
    //assign sCnt8 = (~|(rCnt[2:0])) & (|rCnt[5:3]);
    assign sCnt8 = (~|(rCnt[2:0])) & ((|rCnt[5:3]) | rCntOV);
 
 
    assign sCSn = sOEn & sWRn;
    assign sOEn = ~sRamOE;
    assign sWRn = ~sRamWR;
    assign sDqDir = sRamWR;
 
    always@(posedge spi_sck , posedge spi_cs )begin
        if(spi_cs)begin
            rINBUF <= 'b0;
            rCnt <= 'b0;
        end
        else
        begin
               rINBUF <= {rINBUF[6:0], spi_mosi};
               rCnt <= rCnt + 1'b1;
        end
    end
 
    reg [7:0] rCmd;
    reg [7:0] rState;
    reg [16:0] rAddress;
    reg rReadFlag1,rReadFlag2;
    assign sAddress = (rReadFlag1 ) ? {rAddress[16:8],rINBUF}:rAddress;
 
    reg rDoutEn;
 
    wire sRamOE;
    assign sRamOE = sCnt8 & spi_sck & (rReadFlag1 | rReadFlag2);
 
    reg rWriteFlag1;
    wire sRamWR;
    assign sRamWR = sCnt8 & spi_sck & rWriteFlag1;
 
 
    reg [7:0] rRamWrBuf;
    assign sDqOut = sRamWR?rINBUF:8'h00;
 
    reg rCmdGotFlag;
 
 
    always@( negedge spi_sck , posedge spi_cs  ) begin
 
        if(spi_cs)begin
            rWriteFlag1<= 'b0;
            rReadFlag1<= 'b0;
            rReadFlag2<= 'b0;
            rDoutEn <= 0;
            rAddress<= 'b0;
            rCmdGotFlag <= 0;
            rCntOV <= 1'b0;
        end
        else
        if(sCnt8)begin
            if(!rCmdGotFlag)begin
                rCmdGotFlag <= 1'b1;
                rCntOV <= 1'b1;
                rCmd <= rINBUF;
                if(rINBUF == 8'h9f) rOUTBUF <= 8'haa;
                if(rINBUF == 8'h05) rOUTBUF <= rState;
                if(rINBUF == 8'h04) rState[1] <= 1'b0;
                if(rINBUF == 8'h06) rState[1] <= 1'b1;
            end
            else begin
                case(rCmd)
                8'h01:begin
                    if( rCnt[5:3] == 3'b010) rState <= rINBUF;
                    end
                8'h02:begin
                    if( rWriteFlag1 == 'b0 )begin
                        case( rCnt[5:3])
                        3'b010: begin
                            rAddress[16] <= rINBUF[0];
                        end
                        3'b011: begin
                            rAddress[15:8] <= rINBUF;
                        end
                        3'b100: begin
                            rAddress[7:0] <= rINBUF;
                            rWriteFlag1 <= 1'b1;
                        end
                        endcase
                    end
                    else begin
                        rRamWrBuf <= rINBUF;
                        rAddress <= rAddress + 1'b1;
                    end
 
                    end
                8'h03:begin
                    if( rReadFlag2 == 'b0 )begin
                        case( rCnt[5:3])
                        3'b010: begin
                            rAddress[16] <= rINBUF[0];
                            //rOUTBUF <= 8'h00; 
                            rReadFlag1<= 'b0;
                            rReadFlag2<= 'b0;
                        end
                        3'b011: begin
                            rAddress[15:8] <= rINBUF;
                            //rOUTBUF <= 8'h00; 
                            rReadFlag1<= 'b1;
                            rReadFlag2<= 'b0;
                        end
                        3'b100: begin
                            rAddress[16:0] <= {rAddress[16:8], rINBUF} + 1'b1;
                            rOUTBUF <= sDqIn;
                            rReadFlag1<= 'b0;
                            rReadFlag2 <= 'b1;
                        end
                        endcase
                    end
                    else begin
                        rOUTBUF <= sDqIn;
                        rAddress <= rAddress + 1'b1;
                    end
                    end
                8'h04:begin
 
                    end
                8'h05:begin
                    if( rCnt[5:3] == 3'b010) rOUTBUF <= rState;
                    end
                8'h06:begin
 
                    end
                8'h9f:begin
                        case( rCnt[5:3])
                        3'b010: begin
                            rOUTBUF <= 8'h11;
                        end
                        3'b011: begin
                            rOUTBUF <= 8'h22;
                        end
                        3'b100: begin
                            rOUTBUF <= 8'h33;
                        end
                        endcase
                    end
                 default:begin
 
                    end
                endcase
            end
        end
        else begin
            rOUTBUF <= {rOUTBUF[6:0],1'b0};
        end
    end
      `probe(rCnt);
 
    `probe(rCmd);
    `probe(spi_sck);
    `probe(rINBUF);
    `probe(rOUTBUF);
    `probe(sCnt8);
    `probe(rState);
    `probe(sAddress);
    `probe(rAddress);
    `probe(rReadFlag1);
    `probe(rReadFlag2);
    `probe(sRamOE);
    `probe(sRamWR);
    `probe(rRamWrBuf);
 
    `probe(sCSn);
    `probe(sOEn);
    `probe( sWRn);
    `probe(sDqOut);
    `probe(sDqIn);
 
endmodule

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Subversion Repositories spi2ram

[/] [spi2ram/] [trunk/] [tb2.v] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	longquan	`module top_module ();`
2			`reg clk=0;`
3
4			`reg spi_sck,spi_cs,spi_mosi,spi_clk ;`
5
6			`wire spi_miso;`
7			`wire[16:0] nvram_addr;`
8			`wire nvram_en;`
9			`wire nvram_g;`
10			`wire nvram_w;`
11
12			`reg sys_clk;`
13			`reg sys_rstn;`
14			`reg [7:0] rDin;`
15
16			`parameter clockperiod = 10;`
17			`parameter clockperiod1 = 8;`
18
19			`initial`
20			`begin`
21			`rDin = 0;`
22			`sys_rstn = 0;`
23			`sys_clk = 0;`
24			`#15`
25			`sys_rstn = 1;`
26			`end`
27
28			`initial`
29			`begin`
30			`spi_sck = 1'b0;`
31			`//repeat(1000) spi_sck = #(clockperiod/2)~spi_sck;`
32			`end`
33
34
35			initial `probe_start; // Start the timing diagram
36
37			`// A testbench`
38
39			`initial begin`
40			`#80;`
41			`spi_cs = 1'b0;`
42			`#20;spi_cs = 1'b1;`
43			`#20;spi_cs = 1'b0;`
44			`datasend(8'h03);`
45			`datasend(8'h01);`
46			`datasend(8'h55);`
47			`rDin = 8'h11;`
48			`datasend(8'ha1);`
49			`rDin = 8'h33;`
50			`datasend(8'hdd);`
51			`rDin = 8'h22;`
52			`datasend(8'h11);`
53			`rDin = 8'h77;`
54			`datasend(8'h22);`
55			`rDin = 8'h99;`
56			`datasend(8'h44);`
57
58			`spi_cs = 1'b1;`
59			`#20;`
60
61			`$finish; // Quit the simulation`
62			`end`
63
64
65
66			`task datasend(input [7:0] senddata);`
67			`begin`
68			`#5; spi_sck = 1'b0;`
69			`spi_mosi = senddata[7];`
70			`#5; spi_sck = 1'b1;`
71			`#5; spi_sck = 1'b0;`
72			`spi_mosi = senddata[6];`
73			`#5; spi_sck = 1'b1;`
74			`#5; spi_sck = 1'b0;`
75			`spi_mosi = senddata[5];`
76			`#5; spi_sck = 1'b1;`
77			`#5; spi_sck = 1'b0;`
78			`spi_mosi = senddata[4];`
79			`#5; spi_sck = 1'b1;`
80			`#5; spi_sck = 1'b0;`
81			`spi_mosi = senddata[3];`
82			`#5; spi_sck = 1'b1;`
83			`#5; spi_sck = 1'b0;`
84			`spi_mosi = senddata[2];`
85			`#5; spi_sck = 1'b1;`
86			`#5; spi_sck = 1'b0;`
87			`spi_mosi = senddata[1];`
88			`#5; spi_sck = 1'b1;`
89			`#5; spi_sck = 1'b0;`
90			`spi_mosi = senddata[0];`
91			`#5; spi_sck = 1'b1;`
92			`#5; spi_sck = 1'b0;`
93			`#5;`
94
95			`end`
96			`endtask`
97			`spi_slave_nvram spi_slave_nvram_sim (`
98
99			`.spi_sck(spi_sck),`
100			`.spi_cs(spi_cs),`
101			`.spi_mosi(spi_mosi),`
102			`.spi_miso(spi_miso),`
103
104			`.sAddress(sAddress) ,`
105			`.sCSn(sCSn),`
106			`.sOEn(sOEn),`
107			`.sWRn(sWRn),`
108			`.sDqDir(sDqDir),`
109			`.sDqOut(sDqOut),`
110			`.sDqIn(rDin)`
111			`);`
112
113			`probe(spi_sck); // Probe signal "clk"
114			`probe(spi_mosi); // Probe signal "clk"
115			`probe(sys_rstn); // Probe signal "clk"
116			`probe(spi_cs); // Probe signal "clk"
117			`probe(spi_miso); // Probe signal "clk"
118			`endmodule`
119
120			`module spi_slave_nvram`
121			`(`
122			`//spi interface`
123			`input spi_sck,`
124			`input spi_cs,`
125			`input spi_mosi,`
126			`output spi_miso,`
127			`//nvram interface`
128
129			`output [16:0] sAddress ,`
130			`output sCSn,`
131			`output sOEn,`
132			`output sWRn,`
133			`output sDqDir,`
134			`output [7:0] sDqOut,`
135			`input [7:0] sDqIn`
136			`);`
137
138			`reg [7:0] rINBUF;`
139			`reg [7:0] rOUTBUF;`
140			`assign spi_miso = rOUTBUF[7];`
141
142
143			`reg [5:0] rCnt;`
144			`reg rCntOV;`
145			`wire sCnt8;`
146			`//assign sCnt8 = (~\|(rCnt[2:0])) & (\|rCnt[5:3]);`
147			`assign sCnt8 = (~\|(rCnt[2:0])) & ((\|rCnt[5:3]) \| rCntOV);`
148
149
150			`assign sCSn = sOEn & sWRn;`
151			`assign sOEn = ~sRamOE;`
152			`assign sWRn = ~sRamWR;`
153			`assign sDqDir = sRamWR;`
154
155			`always@(posedge spi_sck , posedge spi_cs )begin`
156			`if(spi_cs)begin`
157			`rINBUF <= 'b0;`
158			`rCnt <= 'b0;`
159			`end`
160			`else`
161			`begin`
162			`rINBUF <= {rINBUF[6:0], spi_mosi};`
163			`rCnt <= rCnt + 1'b1;`
164			`end`
165			`end`
166
167			`reg [7:0] rCmd;`
168			`reg [7:0] rState;`
169			`reg [16:0] rAddress;`
170			`reg rReadFlag1,rReadFlag2;`
171			`assign sAddress = (rReadFlag1 ) ? {rAddress[16:8],rINBUF}:rAddress;`
172
173			`reg rDoutEn;`
174
175			`wire sRamOE;`
176			`assign sRamOE = sCnt8 & spi_sck & (rReadFlag1 \| rReadFlag2);`
177
178			`reg rWriteFlag1;`
179			`wire sRamWR;`
180			`assign sRamWR = sCnt8 & spi_sck & rWriteFlag1;`
181
182
183			`reg [7:0] rRamWrBuf;`
184			`assign sDqOut = sRamWR?rINBUF:8'h00;`
185
186			`reg rCmdGotFlag;`
187
188
189			`always@( negedge spi_sck , posedge spi_cs ) begin`
190
191			`if(spi_cs)begin`
192			`rWriteFlag1<= 'b0;`
193			`rReadFlag1<= 'b0;`
194			`rReadFlag2<= 'b0;`
195			`rDoutEn <= 0;`
196			`rAddress<= 'b0;`
197			`rCmdGotFlag <= 0;`
198			`rCntOV <= 1'b0;`
199			`end`
200			`else`
201			`if(sCnt8)begin`
202			`if(!rCmdGotFlag)begin`
203			`rCmdGotFlag <= 1'b1;`
204			`rCntOV <= 1'b1;`
205			`rCmd <= rINBUF;`
206			`if(rINBUF == 8'h9f) rOUTBUF <= 8'haa;`
207			`if(rINBUF == 8'h05) rOUTBUF <= rState;`
208			`if(rINBUF == 8'h04) rState[1] <= 1'b0;`
209			`if(rINBUF == 8'h06) rState[1] <= 1'b1;`
210			`end`
211			`else begin`
212			`case(rCmd)`
213			`8'h01:begin`
214			`if( rCnt[5:3] == 3'b010) rState <= rINBUF;`
215			`end`
216			`8'h02:begin`
217			`if( rWriteFlag1 == 'b0 )begin`
218			`case( rCnt[5:3])`
219			`3'b010: begin`
220			`rAddress[16] <= rINBUF[0];`
221			`end`
222			`3'b011: begin`
223			`rAddress[15:8] <= rINBUF;`
224			`end`
225			`3'b100: begin`
226			`rAddress[7:0] <= rINBUF;`
227			`rWriteFlag1 <= 1'b1;`
228			`end`
229			`endcase`
230			`end`
231			`else begin`
232			`rRamWrBuf <= rINBUF;`
233			`rAddress <= rAddress + 1'b1;`
234			`end`
235
236			`end`
237			`8'h03:begin`
238			`if( rReadFlag2 == 'b0 )begin`
239			`case( rCnt[5:3])`
240			`3'b010: begin`
241			`rAddress[16] <= rINBUF[0];`
242			`//rOUTBUF <= 8'h00;`
243			`rReadFlag1<= 'b0;`
244			`rReadFlag2<= 'b0;`
245			`end`
246			`3'b011: begin`
247			`rAddress[15:8] <= rINBUF;`
248			`//rOUTBUF <= 8'h00;`
249			`rReadFlag1<= 'b1;`
250			`rReadFlag2<= 'b0;`
251			`end`
252			`3'b100: begin`
253			`rAddress[16:0] <= {rAddress[16:8], rINBUF} + 1'b1;`
254			`rOUTBUF <= sDqIn;`
255			`rReadFlag1<= 'b0;`
256			`rReadFlag2 <= 'b1;`
257			`end`
258			`endcase`
259			`end`
260			`else begin`
261			`rOUTBUF <= sDqIn;`
262			`rAddress <= rAddress + 1'b1;`
263			`end`
264			`end`
265			`8'h04:begin`
266
267			`end`
268			`8'h05:begin`
269			`if( rCnt[5:3] == 3'b010) rOUTBUF <= rState;`
270			`end`
271			`8'h06:begin`
272
273			`end`
274			`8'h9f:begin`
275			`case( rCnt[5:3])`
276			`3'b010: begin`
277			`rOUTBUF <= 8'h11;`
278			`end`
279			`3'b011: begin`
280			`rOUTBUF <= 8'h22;`
281			`end`
282			`3'b100: begin`
283			`rOUTBUF <= 8'h33;`
284			`end`
285			`endcase`
286			`end`
287			`default:begin`
288
289			`end`
290			`endcase`
291			`end`
292			`end`
293			`else begin`
294			`rOUTBUF <= {rOUTBUF[6:0],1'b0};`
295			`end`
296			`end`
297			`probe(rCnt);
298
299			`probe(rCmd);
300			`probe(spi_sck);
301			`probe(rINBUF);
302			`probe(rOUTBUF);
303			`probe(sCnt8);
304			`probe(rState);
305			`probe(sAddress);
306			`probe(rAddress);
307			`probe(rReadFlag1);
308			`probe(rReadFlag2);
309			`probe(sRamOE);
310			`probe(sRamWR);
311			`probe(rRamWrBuf);
312
313			`probe(sCSn);
314			`probe(sOEn);
315			`probe( sWRn);
316			`probe(sDqOut);
317			`probe(sDqIn);
318
319			`endmodule`