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[/] [spi_master_slave/] [trunk/] [rtl/] [spi_master_slave/] [spi_loopback.vhd] - Blame information for rev 24

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1 24 jdoin
----------------------------------------------------------------------------------
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-- Company: 
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-- Engineer: 
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-- 
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-- Create Date:    23:44:37 05/17/2011 
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-- Design Name: 
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-- Module Name:    spi_loopback - Behavioral 
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-- Project Name: 
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-- Target Devices: 
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-- Tool versions: 
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-- Description: 
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--          This is a simple wrapper for the 'spi_master' and 'spi_slave' cores, to synthesize the 2 cores and
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--          test them in the simulator.
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--
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-- Dependencies: 
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--
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-- Revision: 
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-- Revision 0.01 - File Created
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-- Additional Comments: 
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.all;
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entity spi_loopback is
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    Generic (
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        N : positive := 32;                                         -- 32bit serial word length is default
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        CPOL : std_logic := '0';                                    -- SPI mode selection (mode 0 default)
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        CPHA : std_logic := '1';                                    -- CPOL = clock polarity, CPHA = clock phase.
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        PREFETCH : positive := 2;                                   -- prefetch lookahead cycles
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        SPI_2X_CLK_DIV : positive := 5                              -- for a 100MHz sclk_i, yields a 10MHz SCK
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        );
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    Port(
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        ----------------MASTER-----------------------
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        m_clk_i : IN std_logic;
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        m_rst_i : IN std_logic;
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        m_spi_ssel_o : OUT std_logic;
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        m_spi_sck_o : OUT std_logic;
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        m_spi_mosi_o : OUT std_logic;
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        m_spi_miso_i : IN std_logic;
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        m_di_req_o : OUT std_logic;
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        m_di_i : IN std_logic_vector(N-1 downto 0);
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        m_wren_i : IN std_logic;
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        m_do_valid_o : OUT std_logic;
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        m_do_o : OUT std_logic_vector(N-1 downto 0);
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        ----- debug -----
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        m_do_transfer_o : OUT std_logic;
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        m_wren_o : OUT std_logic;
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        m_wren_ack_o : OUT std_logic;
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        m_rx_bit_reg_o : OUT std_logic;
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        m_state_dbg_o : OUT std_logic_vector(5 downto 0);
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        m_core_clk_o : OUT std_logic;
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        m_core_n_clk_o : OUT std_logic;
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        m_sh_reg_dbg_o : OUT std_logic_vector(N-1 downto 0);
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        ----------------SLAVE-----------------------
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        s_clk_i : IN std_logic;
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        s_spi_ssel_i : IN std_logic;
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        s_spi_sck_i : IN std_logic;
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        s_spi_mosi_i : IN std_logic;
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        s_spi_miso_o : OUT std_logic;
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        s_di_req_o : OUT std_logic;                                         -- preload lookahead data request line
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        s_di_i : IN std_logic_vector (N-1 downto 0) := (others => 'X');     -- parallel load data in (clocked in on rising edge of clk_i)
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        s_wren_i : IN std_logic := 'X';                                     -- user data write enable
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        s_do_valid_o : OUT std_logic;                                       -- do_o data valid strobe, valid during one clk_i rising edge.
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        s_do_o : OUT std_logic_vector (N-1 downto 0);                       -- parallel output (clocked out on falling clk_i)
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        ----- debug -----
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        s_do_transfer_o : OUT std_logic;                                    -- debug: internal transfer driver
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        s_wren_o : OUT std_logic;
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        s_wren_ack_o : OUT std_logic;
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        s_rx_bit_reg_o : OUT std_logic;
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        s_state_dbg_o : OUT std_logic_vector (5 downto 0)                   -- debug: internal state register
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--      s_sh_reg_dbg_o : OUT std_logic_vector (N-1 downto 0)                -- debug: internal shift register
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        );
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end spi_loopback;
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architecture Structural of spi_loopback is
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begin
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    --=============================================================================================
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    -- Component instantiation for the SPI master port
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    --=============================================================================================
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    Inst_spi_master: entity work.spi_master(rtl)
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        generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH, SPI_2X_CLK_DIV => SPI_2X_CLK_DIV)
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        port map(
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            sclk_i => m_clk_i,                      -- system clock is used for serial and parallel ports
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            pclk_i => m_clk_i,
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            rst_i => m_rst_i,
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            spi_ssel_o => m_spi_ssel_o,
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            spi_sck_o => m_spi_sck_o,
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            spi_mosi_o => m_spi_mosi_o,
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            spi_miso_i => m_spi_miso_i,
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            di_req_o => m_di_req_o,
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            di_i => m_di_i,
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            wren_i => m_wren_i,
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            do_valid_o => m_do_valid_o,
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            do_o => m_do_o,
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            ----- debug -----
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            do_transfer_o => m_do_transfer_o,
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            wren_o => m_wren_o,
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            wren_ack_o => m_wren_ack_o,
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            rx_bit_reg_o => m_rx_bit_reg_o,
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            state_dbg_o => m_state_dbg_o,
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            core_clk_o => m_core_clk_o,
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            core_n_clk_o => m_core_n_clk_o,
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            sh_reg_dbg_o => m_sh_reg_dbg_o
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        );
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    --=============================================================================================
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    -- Component instantiation for the SPI slave port
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    --=============================================================================================
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    Inst_spi_slave: entity work.spi_slave(rtl)
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        generic map (N => N, CPOL => CPOL, CPHA => CPHA, PREFETCH => PREFETCH)
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        port map(
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            clk_i => s_clk_i,
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            spi_ssel_i => s_spi_ssel_i,
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            spi_sck_i => s_spi_sck_i,
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            spi_mosi_i => s_spi_mosi_i,
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            spi_miso_o => s_spi_miso_o,
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            di_req_o => s_di_req_o,
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            di_i => s_di_i,
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            wren_i => s_wren_i,
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            do_valid_o => s_do_valid_o,
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            do_o => s_do_o,
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            ----- debug -----
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            do_transfer_o => s_do_transfer_o,
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            wren_o => s_wren_o,
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            wren_ack_o => s_wren_ack_o,
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            rx_bit_reg_o => s_rx_bit_reg_o,
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            state_dbg_o => s_state_dbg_o
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--            sh_reg_dbg_o => s_sh_reg_dbg_o
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        );
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end Structural;
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