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[/] [spi_master_slave/] [trunk/] [rtl/] [spi_master_slave/] [spi_loopback_test.vhd] - Blame information for rev 24

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1 24 jdoin
--------------------------------------------------------------------------------
2
-- Company: 
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-- Engineer:        Jonny Doin
4
--
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-- Create Date:     22:59:18 04/25/2011
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-- Design Name:     spi_master_slave
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-- Module Name:     spi_master_slave/spi_loopback_test.vhd
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-- Project Name:    SPI_interface
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-- Target Device:   Spartan-6
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-- Tool versions:   ISE 13.1
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-- Description:     Testbench to simulate the master and slave SPI interfaces. Each module can be tested
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--                  in a "real" environment, where the 'spi_master' exchanges data with the 'spi_slave'
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--                  module, simulating the internal working of each design.
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--                  In behavioral simulation, select a matching data width (N) and spi mode (CPOL, CPHA) for
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--                  both modules, and also a different clock domain for each parallel interface.
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--                  Different values for PREFETCH for each interface can be tested, to model the best value
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--                  for the pipelined memory / bus that is attached to the di/do ports.
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--                  To test the parallel interfaces, a simple ROM memory is simulated for each interface, with
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--                  8 words of data to be sent, synchronous to each clock and flow control signals.
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--
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-- 
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-- VHDL Test Bench Created by ISE for modules: 'spi_master' and 'spi_slave'
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-- 
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-- Dependencies:
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-- 
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.10 - Implemented FIFO simulation for each interface.
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-- Additional Comments:
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--
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-- Notes: 
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation 
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.all;
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ENTITY spi_loopback_test IS
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    GENERIC (
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        N : positive := 32;                                 -- 32bit serial word length is default
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        CPOL : std_logic := '0';                            -- SPI mode selection (mode 0 default)
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        CPHA : std_logic := '1';                            -- CPOL = clock polarity, CPHA = clock phase.
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        PREFETCH : positive := 2                            -- prefetch lookahead cycles
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    );
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END spi_loopback_test;
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ARCHITECTURE behavior OF spi_loopback_test IS
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    --=========================================================
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    -- Component declaration for the Unit Under Test (UUT)
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    --=========================================================
59
 
60
        COMPONENT spi_loopback
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        PORT(
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                m_clk_i : IN std_logic;
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                m_rst_i : IN std_logic;
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                m_spi_miso_i : IN std_logic;
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                m_di_i : IN std_logic_vector(31 downto 0);
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                m_wren_i : IN std_logic;
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                s_clk_i : IN std_logic;
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                s_spi_ssel_i : IN std_logic;
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                s_spi_sck_i : IN std_logic;
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                s_spi_mosi_i : IN std_logic;
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                s_di_i : IN std_logic_vector(31 downto 0);
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                s_wren_i : IN std_logic;
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                m_spi_ssel_o : OUT std_logic;
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                m_spi_sck_o : OUT std_logic;
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                m_spi_mosi_o : OUT std_logic;
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                m_di_req_o : OUT std_logic;
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                m_do_valid_o : OUT std_logic;
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                m_do_o : OUT std_logic_vector(31 downto 0);
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                m_do_transfer_o : OUT std_logic;
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                m_wren_o : OUT std_logic;
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                m_wren_ack_o : OUT std_logic;
82
                m_rx_bit_reg_o : OUT std_logic;
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                m_state_dbg_o : OUT std_logic_vector(5 downto 0);
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                m_core_clk_o : OUT std_logic;
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                m_core_n_clk_o : OUT std_logic;
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                m_sh_reg_dbg_o : OUT std_logic_vector(31 downto 0);
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                s_spi_miso_o : OUT std_logic;
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                s_di_req_o : OUT std_logic;
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                s_do_valid_o : OUT std_logic;
90
                s_do_o : OUT std_logic_vector(31 downto 0);
91
                s_do_transfer_o : OUT std_logic;
92
                s_wren_o : OUT std_logic;
93
                s_wren_ack_o : OUT std_logic;
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                s_rx_bit_reg_o : OUT std_logic;
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                s_state_dbg_o : OUT std_logic_vector(5 downto 0)
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                );
97
        END COMPONENT;
98
 
99
    --=========================================================
100
    -- constants
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    --=========================================================
102
    constant fifo_memory_size : integer := 16;
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104
    --=========================================================
105
    -- types
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    --=========================================================
107
    type fifo_memory_type is array (0 to fifo_memory_size-1) of std_logic_vector (N-1 downto 0);
108
 
109
    --=========================================================
110
    -- signals to connect the instances
111
    --=========================================================
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    -- internal clk and rst
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    signal m_clk : std_logic := '0';                -- clock domain for the master parallel interface. Must be faster than spi bus sck.
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    signal s_clk : std_logic := '0';                -- clock domain for the slave parallel interface. Must be faster than spi bus sck.
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    signal rst : std_logic := 'U';
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    -- spi bus wires
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    signal spi_sck : std_logic;
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    signal spi_ssel : std_logic;
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    signal spi_miso : std_logic;
120
    signal spi_mosi : std_logic;
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    -- master parallel interface
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    signal di_m : std_logic_vector (N-1 downto 0) := (others => '0');
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    signal do_m : std_logic_vector (N-1 downto 0) := (others => 'U');
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    signal do_valid_m : std_logic;
125
    signal do_transfer_m : std_logic;
126
    signal di_req_m : std_logic;
127
    signal wren_m : std_logic := '0';
128
    signal wren_o_m : std_logic := 'U';
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    signal wren_ack_o_m : std_logic := 'U';
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    signal rx_bit_reg_m : std_logic;
131
    signal state_m : std_logic_vector (5 downto 0);
132
    signal core_clk_o_m : std_logic;
133
    signal core_n_clk_o_m : std_logic;
134
    signal sh_reg_m : std_logic_vector (N-1 downto 0) := (others => '0');
135
    -- slave parallel interface
136
    signal di_s : std_logic_vector (N-1 downto 0) := (others => '0');
137
    signal do_s : std_logic_vector (N-1 downto 0);
138
    signal do_valid_s : std_logic;
139
    signal do_transfer_s : std_logic;
140
    signal di_req_s : std_logic;
141
    signal wren_s : std_logic := '0';
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    signal wren_o_s : std_logic := 'U';
143
    signal wren_ack_o_s : std_logic := 'U';
144
    signal rx_bit_reg_s : std_logic;
145
    signal state_s : std_logic_vector (5 downto 0);
146
--    signal sh_reg_s : std_logic_vector (N-1 downto 0);
147
 
148
    --=========================================================
149
    -- Clock period definitions
150
    --=========================================================
151
    constant m_clk_period : time := 10 ns;          -- 100MHz master parallel clock
152
    constant s_clk_period : time := 10 ns;          -- 100MHz slave parallel clock
153
 
154
BEGIN
155
 
156
    --=========================================================
157
    -- Component instantiation for the Unit Under Test (UUT)
158
    --=========================================================
159
 
160
    Inst_spi_loopback: spi_loopback
161
    port map(
162
        ----------------MASTER-----------------------
163
        m_clk_i => m_clk,
164
        m_rst_i => rst,
165
        m_spi_ssel_o => spi_ssel,
166
        m_spi_sck_o => spi_sck,
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        m_spi_mosi_o => spi_mosi,
168
        m_spi_miso_i => spi_miso,
169
        m_di_req_o => di_req_m,
170
        m_di_i => di_m,
171
        m_wren_i => wren_m,
172
        m_do_valid_o => do_valid_m,
173
        m_do_o => do_m,
174
        ----- debug -----
175
        m_do_transfer_o => do_transfer_m,
176
        m_wren_o => wren_o_m,
177
        m_wren_ack_o => wren_ack_o_m,
178
        m_rx_bit_reg_o => rx_bit_reg_m,
179
        m_state_dbg_o => state_m,
180
        m_core_clk_o => core_clk_o_m,
181
        m_core_n_clk_o => core_n_clk_o_m,
182
        m_sh_reg_dbg_o => sh_reg_m,
183
        ----------------SLAVE-----------------------
184
        s_clk_i => s_clk,
185
        s_spi_ssel_i => spi_ssel,
186
        s_spi_sck_i => spi_sck,
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        s_spi_mosi_i => spi_mosi,
188
        s_spi_miso_o => spi_miso,
189
        s_di_req_o => di_req_s,
190
        s_di_i => di_s,
191
        s_wren_i => wren_s,
192
        s_do_valid_o => do_valid_s,
193
        s_do_o => do_s,
194
        ----- debug -----
195
        s_do_transfer_o => do_transfer_s,
196
        s_wren_o => wren_o_s,
197
        s_wren_ack_o => wren_ack_o_s,
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        s_rx_bit_reg_o => rx_bit_reg_s,
199
        s_state_dbg_o => state_s
200
--        s_sh_reg_dbg_o => sh_reg_s
201
    );
202
 
203
    --=========================================================
204
    -- Clock generator processes
205
    --=========================================================
206
    m_clk_process : process
207
    begin
208
        m_clk <= '0';
209
        wait for m_clk_period/2;
210
        m_clk <= '1';
211
        wait for m_clk_period/2;
212
    end process m_clk_process;
213
 
214
    s_clk_process : process
215
    begin
216
        s_clk <= '0';
217
        wait for s_clk_period/2;
218
        s_clk <= '1';
219
        wait for s_clk_period/2;
220
    end process s_clk_process;
221
 
222
    --=========================================================
223
    -- rst_i process
224
    --=========================================================
225
    rst <= '0', '1' after 20 ns, '0' after 100 ns;
226
 
227
    --=========================================================
228
    -- Master interface process
229
    --=========================================================
230
    master_tx_fifo_proc: process is
231
        variable fifo_memory : fifo_memory_type :=
232
            (X"87654321",X"abcdef01",X"faceb007",X"10203049",X"85a5a5a5",X"7aaa5551",X"7adecabe",X"57564789",
233
             X"12345678",X"beefbeef",X"fee1600d",X"f158ba17",X"5ee1a7e3",X"101096da",X"600ddeed",X"deaddead");
234
        variable fifo_head : integer range 0 to fifo_memory_size-1;
235
    begin
236
        -- synchronous rst_i
237
        wait until rst = '1';
238
        wait until m_clk'event and m_clk = '1';
239
        di_m <= (others => '0');
240
        wren_m <= '0';
241
        fifo_head := 0;
242
        wait until rst = '0';
243
        wait until di_req_m = '1';                          -- wait shift register request for data
244
        -- load next fifo contents into shift register
245
        for cnt in 0 to (fifo_memory_size/2)-1 loop
246
            fifo_head := cnt;                               -- pre-compute next pointer 
247
            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
248
            di_m <= fifo_memory(fifo_head);                 -- place data into tx_data input bus
249
            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
250
            wren_m <= '1';                                  -- write data into spi master
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            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
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            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
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            wren_m <= '0';                                  -- remove write enable signal
254
            wait until di_req_m = '1';                      -- wait shift register request for data
255
        end loop;
256
        wait until spi_ssel = '1';
257
        wait for 2000 ns;
258
        for cnt in (fifo_memory_size/2) to fifo_memory_size-1 loop
259
            fifo_head := cnt;                               -- pre-compute next pointer 
260
            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
261
            di_m <= fifo_memory(fifo_head);                 -- place data into tx_data input bus
262
            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
263
            wren_m <= '1';                                  -- write data into spi master
264
            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
265
            wait until m_clk'event and m_clk = '1';         -- sync fifo data load at next rising edge
266
            wren_m <= '0';                                  -- remove write enable signal
267
            wait until di_req_m = '1';                      -- wait shift register request for data
268
        end loop;
269
        wait;
270
    end process master_tx_fifo_proc;
271
 
272
 
273
    --=========================================================
274
    -- Slave interface process
275
    --=========================================================
276
    slave_tx_fifo_proc: process is
277
        variable fifo_memory : fifo_memory_type :=
278
            (X"90201031",X"97640231",X"ef55aaf1",X"babaca51",X"b00b1ee5",X"51525354",X"81828384",X"91929394",
279
             X"be575ec5",X"2fa57410",X"cafed0ce",X"afadab0a",X"bac7ed1a",X"f05fac75",X"2acbac7e",X"12345678");
280
        variable fifo_head : integer range 0 to fifo_memory_size-1;
281
    begin
282
        -- synchronous rst_i
283
        wait until rst = '1';
284
        wait until s_clk'event and s_clk = '1';
285
        di_s <= (others => '0');
286
        wren_s <= '0';
287
        fifo_head := 0;
288
        wait until rst = '0';
289
        wait until di_req_s = '1';                          -- wait shift register request for data
290
        -- load next fifo contents into shift register
291
        for cnt in 0 to fifo_memory_size-1 loop
292
            fifo_head := cnt;                               -- pre-compute next pointer 
293
            wait until s_clk'event and s_clk = '1';         -- sync fifo data load at next rising edge
294
            di_s <= fifo_memory(fifo_head);                 -- place data into tx_data input bus
295
            wait until s_clk'event and s_clk = '1';         -- sync fifo data load at next rising edge
296
            wren_s <= '1';                                  -- write data into shift register
297
            wait until s_clk'event and s_clk = '1';         -- sync fifo data load at next rising edge
298
            wait until s_clk'event and s_clk = '1';         -- sync fifo data load at next rising edge
299
            wren_s <= '0';                                  -- remove write enable signal
300
            wait until di_req_s = '1';                      -- wait shift register request for data
301
        end loop;
302
        wait;
303
    end process slave_tx_fifo_proc;
304
 
305
END ARCHITECTURE behavior;

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