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1 5 jdoin
-----------------------------------------------------------------------------------------------------------------------
2
-- Author:          Jonny Doin, jdoin@opencores.org
3
-- 
4
-- Create Date:     12:18:12 04/25/2011 
5
-- Module Name:     SPI_MASTER - RTL
6
-- Project Name:    SPI MASTER / SLAVE INTERFACE
7
-- Target Devices:  Spartan-6
8
-- Tool versions:   ISE 13.1
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-- Description: 
10
--
11
--      This block is the SPI master interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
13
--      a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
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--      All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
15
--      'sclk_i' clock.
16
--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
17
--      clock domains.
18
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
19
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling 
20
--      ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
21
--
22
--      SPI CLOCK GENERATION
23
--      ====================
24
--
25
--      The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference 
26
--      clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the 
27
--      SPI_2X clock, which is 2x the desired SCK frequency. 
28
--      All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
29
--      at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
30
--      by combinatorial clock dividers outputs.
31
--      The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
32
--
33
--      PARALLEL WRITE INTERFACE
34
--      ========================
35
--      The parallel interface has an input port 'di_i' and an output port 'do_o'.
36
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
37
--      that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the 
38
--      next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
39
--      For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
40
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
41
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
42
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
43
--      if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
44
--      enters idle state and deasserts SSEL.
45
--      When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering 
46
--      idle state, if a previously loaded data has already been transferred.
47
--
48
--      PARALLEL WRITE SEQUENCE
49
--      =======================
50
--                         __    __    __    __    __    __    __ 
51
--      pclk_i          __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
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--                               ___________                        
53
--      di_req_o        ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'pclk_i'
54
--                      ______________ ___________________________...
55
--      di_i            __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
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--                                                 _______                        
57
--      wren_i          __________________________/       \_______...     -- user strobes 'wren_i' for one cycle of 'pclk_i'
58
--                      
59
--
60
--      PARALLEL READ INTERFACE
61
--      =======================
62
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
63 6 jdoin
--      the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
64
--      The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
65 5 jdoin
--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
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--      When the interface is idle, data at the 'do_o' port holds the last word received.
67
--
68
--      PARALLEL READ SEQUENCE
69
--      ======================
70
--                      ______        ______        ______        ______   
71 7 jdoin
--      spi_clk          bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- internal spi 2x base clock
72 5 jdoin
--                      _    __    __    __    __    __    __    __    __  
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--      pclk_i           \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock (may be async to sclk_i)
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--                      _____________ _____________________________________...  -- 1) rx data is transferred to 'do_buffer_reg'
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--      do_o            ___old_data__X__________new_data___________________...  --    after last rx bit, at rising 'spi_clk'.
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--                                                   ____________               
77
--      do_valid_o      ____________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
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--                                                                              --    on the 3rd 'pclk_i' rising edge.
79
--
80
--
81
--      The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
82
--      but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
83
--      of the interface, for full duplex operation.
84
--
85
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
86
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
87
--
88
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
89
--                                                                   
90
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
91 6 jdoin
--                                                                   
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--      Author(s):      Jonny Doin, jdoin@opencores.org
93 6 jdoin
--                                                                   
94 5 jdoin
--      Copyright (C) 2011 Authors and OPENCORES.ORG
95 6 jdoin
--      --------------------------------------------
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--                                                                   
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--      This source file may be used and distributed without restriction provided that this copyright statement is not    
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--      removed from the file and that any derivative work contains the original copyright notice and the associated 
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--      disclaimer. 
100
--                                                                   
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--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
102
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
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--      (at your option) any later version.
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--                                                                   
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--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
107
--      details.
108
--
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--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
110 6 jdoin
--      it from http://www.opencores.org/lgpl.shtml
111 5 jdoin
--                                                                   
112
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
113
--
114
-- 2011/04/28   v0.01.0010  [JD]    shifter implemented as a sequential process. timing problems and async issues in synthesis.
115
-- 2011/05/01   v0.01.0030  [JD]    changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
116
-- 2011/05/05   v0.01.0034  [JD]    added an internal buffer register for rx_data, to allow greater liberty in data load/store.
117
-- 2011/05/08   v0.10.0038  [JD]    increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
118
--                                  logic, based on generics, and do_valid_o signal.
119
-- 2011/05/13   v0.20.0045  [JD]    streamlined signal names, added PREFETCH parameter, added assertions.
120
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
121
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
122
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
123
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
124
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
125
--                                  synthesis LUT overhead in Spartan-6 architecture.
126
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
127
-- 2011/06/12   v0.97.0079  [JD]    streamlined wren_ack for all cases and eliminated unnecessary register resets.
128
-- 2011/06/14   v0.97.0083  [JD]    (bug CPHA effect) : redesigned SCK output circuit.
129
--                                  (minor bug) : removed fsm registers from (not rst_i) chip enable.
130
-- 2011/06/15   v0.97.0086  [JD]    removed master MISO input register, to relax MISO data setup time (to get higher speed).
131
-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
132
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
133
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
134
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
135 6 jdoin
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
136 10 jdoin
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
137 5 jdoin
--
138
-----------------------------------------------------------------------------------------------------------------------
139
--  TODO
140
--  ====
141
--
142
-----------------------------------------------------------------------------------------------------------------------
143
library ieee;
144
use ieee.std_logic_1164.all;
145
use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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148
--================================================================================================================
149 10 jdoin
-- SYNTHESIS CONSIDERATIONS
150
-- ========================
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-- There are several output ports that are used to simulate and verify the core operation. 
152
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
153
-- circuitry. 
154
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
155
-- synthesis tool will remove the receive logic from the generated circuitry.
156
--================================================================================================================
157
 
158
entity spi_master is
159
    Generic (
160
        N : positive := 32;                                             -- 32bit serial word length is default
161
        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
162
        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
163
        PREFETCH : positive := 2;                                       -- prefetch lookahead cycles
164
        SPI_2X_CLK_DIV : positive := 5);                                -- for a 100MHz sclk_i, yields a 10MHz SCK
165
    Port (
166
        sclk_i : in std_logic := 'X';                                   -- high-speed serial interface system clock
167
        pclk_i : in std_logic := 'X';                                   -- high-speed parallel interface system clock
168
        rst_i : in std_logic := 'X';                                    -- reset core
169 7 jdoin
        ---- serial interface ----
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        spi_ssel_o : out std_logic;                                     -- spi bus slave select line
171
        spi_sck_o : out std_logic;                                      -- spi bus sck
172
        spi_mosi_o : out std_logic;                                     -- spi bus mosi output
173
        spi_miso_i : in std_logic := 'X';                               -- spi bus spi_miso_i input
174 7 jdoin
        ---- parallel interface ----
175 5 jdoin
        di_req_o : out std_logic;                                       -- preload lookahead data request line
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        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel data in (clocked on rising spi_clk after last bit)
177 5 jdoin
        wren_i : in std_logic := 'X';                                   -- user data write enable, starts transmission when interface is idle
178 6 jdoin
        do_valid_o : out std_logic;                                     -- do_o data valid signal, valid during one spi_clk rising edge.
179
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked on rising spi_clk after last bit)
180 7 jdoin
        --- debug ports: can be removed or left unconnected for the application circuit ---
181 5 jdoin
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
182
        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
183
        wren_ack_o : out std_logic;                                     -- debug: wren ack from state machine
184
        rx_bit_reg_o : out std_logic;                                   -- debug: internal rx bit
185
        state_dbg_o : out std_logic_vector (5 downto 0);                -- debug: internal state register
186
        core_clk_o : out std_logic;
187
        core_n_clk_o : out std_logic;
188
        core_ce_o : out std_logic;
189
        core_n_ce_o : out std_logic;
190
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
191
    );
192
end spi_master;
193
 
194
--================================================================================================================
195
-- this architecture is a pipelined register-transfer description.
196 6 jdoin
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
197 5 jdoin
--================================================================================================================
198 10 jdoin
architecture RTL of spi_master is
199 6 jdoin
    -- core clocks, generated from 'sclk_i': initialized to differential values
200 5 jdoin
    signal core_clk : std_logic := '0';     -- continuous core clock, positive logic
201
    signal core_n_clk : std_logic := '1';   -- continuous core clock, negative logic
202
    signal core_ce : std_logic := '0';      -- core clock enable, positive logic
203
    signal core_n_ce : std_logic := '1';    -- core clock enable, negative logic
204
    -- spi bus clock, generated from the CPOL selected core clock polarity
205
    signal spi_2x_ce : std_logic := '1';    -- spi_2x clock enable
206
    signal spi_clk : std_logic := '0';      -- spi bus output clock
207
    signal spi_clk_reg : std_logic := '0';  -- output pipeline delay for spi sck
208
    -- core fsm clock enables
209
    signal fsm_ce : std_logic := '1';       -- fsm clock enable
210
    signal samp_ce : std_logic := '1';      -- data sampling clock enable
211
    --
212
    -- GLOBAL RESET: 
213
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
214
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
215 7 jdoin
    --      especially for the Spartan-6 and newer CLB architectures, where a async reset can
216 5 jdoin
    --      reduce the usability of the slice registers, due to the need to share the control 
217
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
218 7 jdoin
    --      By using GSR for the initialization, and reducing async RESET local init to the bare
219 5 jdoin
    --      essential, the model achieves better LUT/FF packing and CLB usability.
220
    --
221
    -- internal state signals for register and combinatorial stages
222
    signal state_next : natural range N+1 downto 0 := 0;
223
    signal state_reg : natural range N+1 downto 0 := 0;
224
    -- shifter signals for register and combinatorial stages
225
    signal sh_next : std_logic_vector (N-1 downto 0) := (others => '0');
226
    signal sh_reg : std_logic_vector (N-1 downto 0) := (others => '0');
227
    -- input bit sampled buffer
228
    signal rx_bit_reg : std_logic := '0';
229
    -- buffered di_i data signals for register and combinatorial stages
230
    signal di_reg : std_logic_vector (N-1 downto 0) := (others => '0');
231
    -- internal wren_i stretcher for fsm combinatorial stage
232
    signal wren : std_logic := '0';
233
    signal wren_ack_next : std_logic := '0';
234
    signal wren_ack_reg : std_logic := '0';
235
    -- internal SSEL enable control signals
236
    signal ena_ssel_next : std_logic := '0';
237
    signal ena_ssel_reg : std_logic := '0';
238
    -- internal SCK enable control signals
239
    signal ena_sck_next : std_logic := '0';
240
    signal ena_sck_reg : std_logic := '0';
241
    -- buffered do_o data signals for register and combinatorial stages
242
    signal do_buffer_next : std_logic_vector (N-1 downto 0) := (others => '0');
243
    signal do_buffer_reg : std_logic_vector (N-1 downto 0) := (others => '0');
244
    -- internal signal to flag transfer to do_buffer_reg
245
    signal do_transfer_next : std_logic := '0';
246
    signal do_transfer_reg : std_logic := '0';
247
    -- internal input data request signal 
248
    signal di_req_next : std_logic := '0';
249
    signal di_req_reg : std_logic := '0';
250
    -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
251
    signal do_valid_A : std_logic := '0';
252
    signal do_valid_B : std_logic := '0';
253
    signal do_valid_C : std_logic := '0';
254
    signal do_valid_D : std_logic := '0';
255
    signal do_valid_next : std_logic := '0';
256
    signal do_valid_o_reg : std_logic := '0';
257
    -- cross-clock di_req_reg -> di_req_o_reg pipeline
258
    signal di_req_o_A : std_logic := '0';
259
    signal di_req_o_B : std_logic := '0';
260
    signal di_req_o_C : std_logic := '0';
261
    signal di_req_o_D : std_logic := '0';
262
    signal di_req_o_next : std_logic := '1';
263
    signal di_req_o_reg : std_logic := '1';
264
begin
265
    --=============================================================================================
266
    --  GENERICS CONSTRAINTS CHECKING
267
    --=============================================================================================
268
    -- minimum word width is 8 bits
269 6 jdoin
    assert N >= 8
270
    report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
271 5 jdoin
    severity FAILURE;
272
    -- minimum prefetch lookahead check
273 6 jdoin
    assert PREFETCH >= 2
274
    report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
275 5 jdoin
    severity FAILURE;
276
    -- maximum prefetch lookahead check
277 6 jdoin
    assert PREFETCH <= N-5
278
    report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
279 5 jdoin
    severity FAILURE;
280
    -- SPI_2X_CLK_DIV clock divider value must not be zero
281 6 jdoin
    assert SPI_2X_CLK_DIV > 0
282
    report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
283 5 jdoin
    severity FAILURE;
284
 
285
    --=============================================================================================
286
    --  CLOCK GENERATION
287
    --=============================================================================================
288
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
289
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
290
    -- the spi clock generator and the input sampling clock.
291
    -- The clock generation block derive 2 continuous antiphase signals from the 2x spi base clock 
292
    -- for the core clocking.
293
    -- The 2 clock phases are generated by sepparate and synchronous FFs, and should have only 
294 7 jdoin
    -- differential interconnect delay skew.
295 5 jdoin
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
296
    -- enables are used to control clocking of all internal synchronous circuitry. 
297
    -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, 
298
    -- based on the configuration of CPOL and CPHA.
299
    -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
300
    -- modes, by a single high-speed global clock, preserving clock resources.
301
    -----------------------------------------------------------------------------------------------
302 6 jdoin
    -- generate the 2x spi base clock enable from the serial high-speed input clock
303 5 jdoin
    spi_2x_ce_gen_proc: process (sclk_i) is
304
        variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
305
    begin
306
        if sclk_i'event and sclk_i = '1' then
307
            if clk_cnt = SPI_2X_CLK_DIV-1 then
308
                spi_2x_ce <= '1';
309
                clk_cnt := 0;
310
            else
311
                spi_2x_ce <= '0';
312
                clk_cnt := clk_cnt + 1;
313
            end if;
314
        end if;
315
    end process spi_2x_ce_gen_proc;
316
    -----------------------------------------------------------------------------------------------
317 6 jdoin
    -- generate the core antiphase clocks and clock enables from the 2x base CE.
318 5 jdoin
    core_clock_gen_proc : process (sclk_i) is
319
    begin
320
        if sclk_i'event and sclk_i = '1' then
321
            if spi_2x_ce = '1' then
322
                -- generate the 2 antiphase core clocks
323
                core_clk <= core_n_clk;
324
                core_n_clk <= not core_n_clk;
325
                -- generate the 2 phase core clock enables
326
                core_ce <= core_n_clk;
327
                core_n_ce <= not core_n_clk;
328
            else
329
                core_ce <= '0';
330
                core_n_ce <= '0';
331
            end if;
332
        end if;
333
    end process core_clock_gen_proc;
334
    -----------------------------------------------------------------------------------------------
335
    -- spi clk generator: generate spi_clk from core_clk depending on CPOL
336
    spi_sck_cpol_0_proc :
337
        if CPOL = '0' generate
338
        begin
339
            spi_clk <= core_clk;            -- for CPOL=0, spi clk has idle LOW
340
        end generate;
341
    spi_sck_cpol_1_proc :
342
        if CPOL = '1' generate
343
        begin
344
            spi_clk <= core_n_clk;          -- for CPOL=1, spi clk has idle HIGH
345
        end generate;
346
    -----------------------------------------------------------------------------------------------
347
    -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
348
    -- always sample data at the half-cycle of the fsm update cell
349
    samp_ce_cpha_0_proc :
350
        if CPHA = '0' generate
351
        begin
352
            samp_ce <= core_ce;
353
        end generate;
354
    samp_ce_cpha_1_proc :
355
        if CPHA = '1' generate
356
        begin
357
            samp_ce <= core_n_ce;
358
        end generate;
359
    -----------------------------------------------------------------------------------------------
360 6 jdoin
    -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
361 5 jdoin
    fsm_ce_cpha_0_proc :
362
        if CPHA = '0' generate
363
        begin
364
            fsm_ce <= core_n_ce;            -- for CPHA=0, latch registers at rising edge of negative core clock enable
365
        end generate;
366
    fsm_ce_cpha_1_proc :
367
        if CPHA = '1' generate
368
        begin
369
            fsm_ce <= core_ce;              -- for CPHA=1, latch registers at rising edge of positive core clock enable
370
        end generate;
371
 
372
    --=============================================================================================
373
    --  REGISTERED INPUTS
374
    --=============================================================================================
375
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
376
    --
377
    --  ATTENTION:  REMOVING THE FLIPFLOP (DIRECT CONNECTION) WE GET HIGHER PERFORMANCE DUE TO 
378
    --              REDUCED DEMAND ON MISO SETUP TIME. 
379
    --
380 10 jdoin
    rx_bit_proc : process (sclk_i, spi_miso_i) is
381 5 jdoin
    begin
382 10 jdoin
--        if sclk_i'event and sclk_i = '1' then
383
--            if samp_ce = '1' then
384 5 jdoin
                rx_bit_reg <= spi_miso_i;
385 10 jdoin
--            end if;
386
--        end if;
387 5 jdoin
    end process rx_bit_proc;
388
 
389
    --=============================================================================================
390
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
391
    --=============================================================================================
392
    -- do_valid_o and di_req_o strobe output logic
393
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
394
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
395
    out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
396
                                  do_valid_A, do_valid_B, do_valid_D,
397
                                  di_req_o_A, di_req_o_B, di_req_o_D ) is
398
    begin
399
        if pclk_i'event and pclk_i = '1' then               -- clock at parallel port clock
400
            -- do_transfer_reg -> do_valid_o_reg
401
            do_valid_A <= do_transfer_reg;                  -- the input signal must be at least 2 clocks long
402
            do_valid_B <= do_valid_A;                       -- feed it to a ripple chain of FFDs
403
            do_valid_C <= do_valid_B;
404
            do_valid_D <= do_valid_C;
405
            do_valid_o_reg <= do_valid_next;                -- registered output pulse
406
            --------------------------------
407
            -- di_req_reg -> di_req_o_reg
408
            di_req_o_A <= di_req_reg;                       -- the input signal must be at least 2 clocks long
409
            di_req_o_B <= di_req_o_A;                       -- feed it to a ripple chain of FFDs
410
            di_req_o_C <= di_req_o_B;
411
            di_req_o_D <= di_req_o_C;
412
            di_req_o_reg <= di_req_o_next;                  -- registered output pulse
413
        end if;
414
        -- generate a 2-clocks pulse at the 3rd clock cycle
415
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
416
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
417
    end process out_transfer_proc;
418
    -- parallel load input registers: data register and write enable
419
    in_transfer_proc: process ( pclk_i, wren_i, wren_ack_reg ) is
420
    begin
421
        -- registered data input, input register with clock enable
422
        if pclk_i'event and pclk_i = '1' then
423
            if wren_i = '1' then
424
                di_reg <= di_i;                             -- parallel data input buffer register
425
            end if;
426
        end  if;
427
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
428
        if pclk_i'event and pclk_i = '1' then
429
            if wren_i = '1' then                            -- wren_i is the sync preset for wren
430
                wren <= '1';
431
            elsif wren_ack_reg = '1' then                   -- wren_ack is the sync reset for wren
432
                wren <= '0';
433
            end if;
434
        end  if;
435
    end process in_transfer_proc;
436
 
437
    --=============================================================================================
438 7 jdoin
    --  RTL REGISTER PROCESSES
439
    --=============================================================================================
440
    -- fsm state and data registers: synchronous to the spi base reference clock
441
    core_reg_proc : process (sclk_i) is
442
    begin
443
        -- FF registers clocked on rising edge and cleared on sync rst_i
444
        if sclk_i'event and sclk_i = '1' then
445
            if rst_i = '1' then                             -- sync reset
446
                state_reg <= 0;                             -- only provide local reset for the state machine
447
            elsif fsm_ce = '1' then                         -- fsm_ce is clock enable for the fsm
448
                state_reg <= state_next;                    -- state register
449
            end if;
450
        end if;
451
        -- FF registers clocked on rising edge
452
        if sclk_i'event and sclk_i = '1' then
453
            if fsm_ce = '1' then
454
                sh_reg <= sh_next;                          -- shift register
455
                ena_ssel_reg <= ena_ssel_next;              -- spi select enable
456
                ena_sck_reg <= ena_sck_next;                -- spi clock enable
457
                do_buffer_reg <= do_buffer_next;            -- registered output data buffer 
458
                do_transfer_reg <= do_transfer_next;        -- output data transferred to buffer
459
                di_req_reg <= di_req_next;                  -- input data request
460
                wren_ack_reg <= wren_ack_next;              -- wren ack for data load synchronization
461
            end if;
462
        end if;
463
    end process core_reg_proc;
464
 
465
    --=============================================================================================
466 5 jdoin
    --  RTL combinatorial LOGIC PROCESSES
467
    --=============================================================================================
468
    -- state and datapath combinatorial logic
469
    core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ena_ssel_reg, ena_sck_reg, do_buffer_reg,
470
                                do_transfer_reg, di_reg, wren ) is
471
    begin
472
        sh_next <= sh_reg;                                              -- all output signals are assigned to (avoid latches)
473
        ena_ssel_next <= ena_ssel_reg;                                  -- controls the slave select line
474
        ena_sck_next <= ena_sck_reg;                                    -- controls the clock enable of spi sck line
475
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
476
        do_transfer_next <= do_transfer_reg;                            -- output data flag
477
        wren_ack_next <= '0';                                           -- remove data load ack for all but the load stages
478
        di_req_next <= '0';                                             -- prefetch data request: deassert when shifting data
479
        spi_mosi_o <= sh_reg(N-1);                                      -- shift out tx bit from the MSb
480
        state_next <= state_reg - 1;                                    -- update next state at each sck pulse
481
        case state_reg is
482
            when (N+1) =>                                               -- this state is to enable SSEL before SCK
483
                ena_ssel_next <= '1';                                   -- tx in progress: will assert SSEL
484
                ena_sck_next <= '1';                                    -- enable SCK on next cycle (stays off on first SSEL clock cycle)
485
            when (N) =>                                                 -- deassert 'di_rdy'
486
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
487
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
488
            when (N-1) downto (PREFETCH+3) =>                           -- if rx data is valid, raise 'do_valid'. remove 'do_transfer'
489
                do_transfer_next <= '0';                                -- reset transfer signal
490
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
491
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
492
            when (PREFETCH+2) downto 2 =>                               -- raise prefetch 'di_req_o_next' signal and remove 'do_valid'
493
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
494
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
495
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
496
            when 1 =>                                                   -- transfer rx data to do_buffer and restart if wren
497
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
498
                do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0);   -- shift rx data directly into rx buffer
499
                do_buffer_next(0) <= rx_bit_reg;                        -- shift last rx bit into rx buffer
500
                do_transfer_next <= '1';                                -- signal transfer to do_buffer
501
                if wren = '1' then                                      -- load tx register if valid data present at di_i
502
                    state_next <= N;                                    -- next state is top bit of new data
503
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
504
                    ena_sck_next <= '1';                                -- SCK enabled
505
                    wren_ack_next <= '1';                               -- acknowledge data in transfer
506
                else
507
                    ena_sck_next <= '0';                                -- SCK disabled: tx empty, no data to send
508
                end if;
509
            when 0 =>
510
                di_req_next <= '1';                                     -- will request data if shifter empty
511
                ena_sck_next <= '0';                                    -- SCK disabled: tx empty, no data to send
512
                if wren = '1' then                                      -- load tx register if valid data present at di_i
513
                    ena_ssel_next <= '1';                               -- enable interface SSEL
514
                    state_next <= N+1;                                  -- start from idle: let one cycle for SSEL settling
515
                    spi_mosi_o <= di_reg(N-1);                          -- special case: shift out first tx bit from the MSb (look ahead)
516
                    sh_next <= di_reg;                                  -- load bits from di_reg into shifter
517
                    wren_ack_next <= '1';                               -- acknowledge data in transfer
518
                else
519
                    ena_ssel_next <= '0';                               -- deassert SSEL: interface is idle
520
                    state_next <= 0;                                    -- when idle, keep this state
521
                end if;
522
            when others =>
523
                state_next <= 0;                                        -- state 0 is safe state
524
        end case;
525
    end process core_combi_proc;
526
 
527
    --=============================================================================================
528
    --  OUTPUT LOGIC PROCESSES
529
    --=============================================================================================
530
    -- data output processes
531
    spi_ssel_o_proc:    spi_ssel_o <= not ena_ssel_reg;                 -- drive active-low slave select line 
532
    do_o_proc :         do_o <= do_buffer_reg;                          -- do_o always available
533
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                   -- copy registered do_valid_o to output
534
    di_req_o_proc:      di_req_o <= di_req_o_reg;                       -- copy registered di_req_o to output
535
    -----------------------------------------------------------------------------------------------
536
    -- SCK out logic: pipeline phase compensation for the SCK line
537
    -----------------------------------------------------------------------------------------------
538
    -- This is a MUX with an output register. The register gives us a pipeline delay for the SCK line,
539
    -- enabling higher SCK frequency. The MOSI and SCK phase are compensated by the pipeline delay.
540
    spi_sck_o_gen_proc : process (sclk_i, ena_sck_reg, spi_clk, spi_clk_reg) is
541
    begin
542
        if sclk_i'event and sclk_i = '1' then
543
            if ena_sck_reg = '1' then
544
                spi_clk_reg <= spi_clk;                                 -- copy the selected clock polarity
545
            else
546
                spi_clk_reg <= CPOL;                                    -- when clock disabled, set to idle polarity
547
            end if;
548
        end if;
549
        spi_sck_o <= spi_clk_reg;                                       -- connect register to output
550
    end process spi_sck_o_gen_proc;
551
 
552
    --=============================================================================================
553
    --  DEBUG LOGIC PROCESSES
554
    --=============================================================================================
555
    -- these signals are useful for verification, and can be deleted or commented-out after debug.
556
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
557
    state_dbg_proc:     state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 6)); -- export internal state to debug
558
    rx_bit_reg_proc:    rx_bit_reg_o <= rx_bit_reg;
559
    wren_o_proc:        wren_o <= wren;
560
    wren_ack_o_proc:    wren_ack_o <= wren_ack_reg;
561
    sh_reg_dbg_proc:    sh_reg_dbg_o <= sh_reg;                         -- export sh_reg to debug
562
    core_clk_o_proc:    core_clk_o <= core_clk;
563
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
564
    core_ce_o_proc:     core_ce_o <= core_ce;
565
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
566
 
567 10 jdoin
end architecture RTL;
568 5 jdoin
 

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