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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master.vhd] - Blame information for rev 23

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2 12 jdoin
-- Author:          Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
3 5 jdoin
-- 
4
-- Create Date:     12:18:12 04/25/2011 
5
-- Module Name:     SPI_MASTER - RTL
6
-- Project Name:    SPI MASTER / SLAVE INTERFACE
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-- Target Devices:  Spartan-6
8
-- Tool versions:   ISE 13.1
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-- Description: 
10
--
11
--      This block is the SPI master interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the 'sclk_i', and a spi base clock is generated by dividing sclk_i downto
13
--      a frequency that is 2x the spi SCK line frequency. The divider value is passed as a generic parameter during instantiation.
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--      All parallel i/o interface operations are synchronous to the 'pclk_i' high speed clock, that can be asynchronous to the serial
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--      'sclk_i' clock.
16 13 jdoin
--      For optimized use of longlines, connect 'sclk_i' and 'pclk_i' to the same global clock line.
17 5 jdoin
--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
18
--      clock domains.
19
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
20
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), lookahead prefetch signaling 
21
--      ('PREFETCH'), and spi base clock division from sclk_i ('SPI_2X_CLK_DIV').
22
--
23
--      SPI CLOCK GENERATION
24
--      ====================
25
--
26
--      The clock generation for the SPI SCK is derived from the high-speed 'sclk_i' clock. The core divides this reference 
27
--      clock to form the SPI base clock, by the 'SPI_2X_CLK_DIV' generic parameter. The user must set the divider value for the 
28
--      SPI_2X clock, which is 2x the desired SCK frequency. 
29
--      All registers in the core are clocked by the high-speed clocks, and clock enables are used to run the FSM and other logic
30
--      at lower rates. This architecture preserves FPGA clock resources like global clock buffers, and avoids path delays caused
31
--      by combinatorial clock dividers outputs.
32
--      The core has async clock domain circuitry to handle asynchronous clocks for the SPI and parallel interfaces.
33
--
34
--      PARALLEL WRITE INTERFACE
35
--      ========================
36
--      The parallel interface has an input port 'di_i' and an output port 'do_o'.
37
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 'di_req_o' is a look ahead data request line,
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--      that is set 'PREFETCH' clock cycles in advance to synchronize a pipelined memory or fifo to present the 
39
--      next input data at 'di_i' in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
40
--      For a pipelined sync RAM, a PREFETCH of 2 cycles allows an address generator to present the new adress to the RAM in one
41
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the shifter.
42
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
43
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last SPI clock cycle,
44
--      if continuous transmission is intended. If 'wren_i' is not valid 2 SPI clock cycles after the last transmitted bit, the interface
45
--      enters idle state and deasserts SSEL.
46
--      When the interface is idle, 'wren_i' write strobe loads the data and starts transmission. 'di_req_o' will strobe when entering 
47
--      idle state, if a previously loaded data has already been transferred.
48
--
49
--      PARALLEL WRITE SEQUENCE
50
--      =======================
51
--                         __    __    __    __    __    __    __ 
52
--      pclk_i          __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
53
--                               ___________                        
54
--      di_req_o        ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'pclk_i'
55
--                      ______________ ___________________________...
56
--      di_i            __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'pclk_i' rising edge
57
--                                                 _______                        
58
--      wren_i          __________________________/       \_______...     -- user strobes 'wren_i' for one cycle of 'pclk_i'
59
--                      
60
--
61
--      PARALLEL READ INTERFACE
62
--      =======================
63
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete word is received,
64 6 jdoin
--      the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_clk'.
65
--      The signal 'do_valid_o' is set one 'spi_clk' clock after, to directly drive a synchronous memory or fifo write enable.
66 5 jdoin
--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'pclk_i'.
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--      When the interface is idle, data at the 'do_o' port holds the last word received.
68
--
69
--      PARALLEL READ SEQUENCE
70
--      ======================
71
--                      ______        ______        ______        ______   
72 7 jdoin
--      spi_clk          bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- internal spi 2x base clock
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--                      _    __    __    __    __    __    __    __    __  
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--      pclk_i           \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock (may be async to sclk_i)
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--                      _____________ _____________________________________...  -- 1) rx data is transferred to 'do_buffer_reg'
76 6 jdoin
--      do_o            ___old_data__X__________new_data___________________...  --    after last rx bit, at rising 'spi_clk'.
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--                                                   ____________               
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--      do_valid_o      ____________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'pclk_i' cycles
79
--                                                                              --    on the 3rd 'pclk_i' rising edge.
80
--
81
--
82
--      The propagation delay of spi_sck_o and spi_mosi_o, referred to the internal clock, is balanced by similar path delays,
83
--      but the sampling delay of spi_miso_i imposes a setup time referred to the sck signal that limits the high frequency
84
--      of the interface, for full duplex operation.
85
--
86
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
87
--      The VHDL dialect used is VHDL'93, accepted largely by all synthesis tools.
88
--
89
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
90
--                                                                   
91
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave
92 6 jdoin
--                                                                   
93 23 jdoin
--      Author(s):      Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com
94 6 jdoin
--                                                                   
95 23 jdoin
--      Copyright (C) 2011 Jonny Doin
96
--      -----------------------------
97 6 jdoin
--                                                                   
98
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
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--      removed from the file and that any derivative work contains the original copyright notice and the associated 
100 6 jdoin
--      disclaimer. 
101
--                                                                   
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--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
103
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
104 6 jdoin
--      (at your option) any later version.
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--                                                                   
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--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
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--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
108
--      details.
109
--
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--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
111 23 jdoin
--      it from http://www.gnu.org/licenses/lgpl.txt
112 5 jdoin
--                                                                   
113
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
114
--
115
-- 2011/04/28   v0.01.0010  [JD]    shifter implemented as a sequential process. timing problems and async issues in synthesis.
116
-- 2011/05/01   v0.01.0030  [JD]    changed original shifter design to a fully pipelined RTL fsmd. solved all synthesis issues.
117
-- 2011/05/05   v0.01.0034  [JD]    added an internal buffer register for rx_data, to allow greater liberty in data load/store.
118
-- 2011/05/08   v0.10.0038  [JD]    increased one state to have SSEL start one cycle before SCK. Implemented full CPOL/CPHA
119
--                                  logic, based on generics, and do_valid_o signal.
120
-- 2011/05/13   v0.20.0045  [JD]    streamlined signal names, added PREFETCH parameter, added assertions.
121
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
122
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
123
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
124
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
125
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce
126
--                                  synthesis LUT overhead in Spartan-6 architecture.
127
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
128 12 jdoin
-- 2011/06/12   v0.97.0079  [JD]    streamlined wr_ack for all cases and eliminated unnecessary register resets.
129 5 jdoin
-- 2011/06/14   v0.97.0083  [JD]    (bug CPHA effect) : redesigned SCK output circuit.
130
--                                  (minor bug) : removed fsm registers from (not rst_i) chip enable.
131
-- 2011/06/15   v0.97.0086  [JD]    removed master MISO input register, to relax MISO data setup time (to get higher speed).
132
-- 2011/07/09   v1.00.0095  [JD]    changed all clocking scheme to use a single high-speed clock with clock enables to control lower 
133
--                                  frequency sequential circuits, to preserve clocking resources and avoid path delay glitches.
134
-- 2011/07/10   v1.00.0098  [JD]    implemented SCK clock divider circuit to generate spi clock directly from system clock.
135
-- 2011/07/10   v1.10.0075  [JD]    verified spi_master_slave in silicon at 50MHz, 25MHz, 16.666MHz, 12.5MHz, 10MHz, 8.333MHz, 
136 6 jdoin
--                                  7.1428MHz, 6.25MHz, 1MHz and 500kHz. The core proved very robust at all tested frequencies.
137 10 jdoin
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
138 11 jdoin
-- 2011/07/17   v1.11.0080  [JD]    BUG: CPOL='1', CPHA='1' @50MHz causes MOSI to be shifted one bit earlier.
139
--                                  BUG: CPOL='0', CPHA='1' causes SCK to have one extra pulse with one sclk_i width at the end.
140
-- 2011/07/18   v1.12.0105  [JD]    CHG: spi sck output register changed to remove glitch at last clock when CPHA='1'.
141
--                                  for CPHA='1', max spi clock is 25MHz. for CPHA= '0', max spi clock is >50MHz.
142 12 jdoin
-- 2011/07/24   v1.13.0125  [JD]    FIX: 'sck_ena_ce' is on half-cycle advanced to 'fsm_ce', elliminating CPHA='1' glitches.
143
--                                  Core verified for all CPOL, CPHA at up to 50MHz, simulates to over 100MHz.
144
-- 2011/07/29   v1.14.0130  [JD]    Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
145
--                                  for each state, to avoid reported inference problems in some synthesis engines.
146
--                                  Streamlined port names and indentation blocks.
147 13 jdoin
-- 2011/08/01   v1.15.0135  [JD]    Fixed latch inference for spi_mosi_o driver at the fsm.
148
--                                  The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
149 16 jdoin
-- 2011/08/04   v1.15.0136  [JD]    Fixed assertions (PREFETCH >= 1) and minor comment bugs.
150 5 jdoin
--
151
-----------------------------------------------------------------------------------------------------------------------
152
--  TODO
153
--  ====
154
--
155
-----------------------------------------------------------------------------------------------------------------------
156
library ieee;
157
use ieee.std_logic_1164.all;
158
use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
160 5 jdoin
 
161
--================================================================================================================
162 10 jdoin
-- SYNTHESIS CONSIDERATIONS
163
-- ========================
164 5 jdoin
-- There are several output ports that are used to simulate and verify the core operation. 
165
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
166
-- circuitry. 
167
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
168
-- synthesis tool will remove the receive logic from the generated circuitry.
169 22 jdoin
-- Alternatively, you can remove these ports and related circuitry once the core is verified and
170
-- integrated to your circuit.
171 5 jdoin
--================================================================================================================
172
 
173
entity spi_master is
174
    Generic (
175
        N : positive := 32;                                             -- 32bit serial word length is default
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        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
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        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
178
        PREFETCH : positive := 2;                                       -- prefetch lookahead cycles
179
        SPI_2X_CLK_DIV : positive := 5);                                -- for a 100MHz sclk_i, yields a 10MHz SCK
180
    Port (
181
        sclk_i : in std_logic := 'X';                                   -- high-speed serial interface system clock
182
        pclk_i : in std_logic := 'X';                                   -- high-speed parallel interface system clock
183
        rst_i : in std_logic := 'X';                                    -- reset core
184 7 jdoin
        ---- serial interface ----
185 5 jdoin
        spi_ssel_o : out std_logic;                                     -- spi bus slave select line
186
        spi_sck_o : out std_logic;                                      -- spi bus sck
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        spi_mosi_o : out std_logic;                                     -- spi bus mosi output
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        spi_miso_i : in std_logic := 'X';                               -- spi bus spi_miso_i input
189 7 jdoin
        ---- parallel interface ----
190 5 jdoin
        di_req_o : out std_logic;                                       -- preload lookahead data request line
191 6 jdoin
        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel data in (clocked on rising spi_clk after last bit)
192 5 jdoin
        wren_i : in std_logic := 'X';                                   -- user data write enable, starts transmission when interface is idle
193 12 jdoin
        wr_ack_o : out std_logic;                                       -- write acknowledge
194 6 jdoin
        do_valid_o : out std_logic;                                     -- do_o data valid signal, valid during one spi_clk rising edge.
195
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked on rising spi_clk after last bit)
196 7 jdoin
        --- debug ports: can be removed or left unconnected for the application circuit ---
197 12 jdoin
        sck_ena_o : out std_logic;                                      -- debug: internal sck enable signal
198
        sck_ena_ce_o : out std_logic;                                   -- debug: internal sck clock enable signal
199 5 jdoin
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
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        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
201
        rx_bit_reg_o : out std_logic;                                   -- debug: internal rx bit
202 13 jdoin
        state_dbg_o : out std_logic_vector (3 downto 0);                -- debug: internal state register
203 5 jdoin
        core_clk_o : out std_logic;
204
        core_n_clk_o : out std_logic;
205
        core_ce_o : out std_logic;
206
        core_n_ce_o : out std_logic;
207
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
208
    );
209
end spi_master;
210
 
211
--================================================================================================================
212
-- this architecture is a pipelined register-transfer description.
213 6 jdoin
-- all signals are clocked at the rising edge of the system clock 'sclk_i'.
214 5 jdoin
--================================================================================================================
215 13 jdoin
architecture rtl of spi_master is
216 22 jdoin
    -- core clocks, generated from 'sclk_i': initialized at GSR to differential values
217 11 jdoin
    signal core_clk     : std_logic := '0';     -- continuous core clock, positive logic
218
    signal core_n_clk   : std_logic := '1';     -- continuous core clock, negative logic
219
    signal core_ce      : std_logic := '0';     -- core clock enable, positive logic
220
    signal core_n_ce    : std_logic := '1';     -- core clock enable, negative logic
221 5 jdoin
    -- spi bus clock, generated from the CPOL selected core clock polarity
222 11 jdoin
    signal spi_2x_ce    : std_logic := '1';     -- spi_2x clock enable
223
    signal spi_clk      : std_logic := '0';     -- spi bus output clock
224 12 jdoin
    signal spi_clk_reg  : std_logic;            -- output pipeline delay for spi sck (do NOT global initialize)
225 5 jdoin
    -- core fsm clock enables
226 11 jdoin
    signal fsm_ce       : std_logic := '1';     -- fsm clock enable
227 12 jdoin
    signal sck_ena_ce   : std_logic := '1';     -- SCK clock enable
228 11 jdoin
    signal samp_ce      : std_logic := '1';     -- data sampling clock enable
229 5 jdoin
    --
230
    -- GLOBAL RESET: 
231
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
232
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
233 7 jdoin
    --      especially for the Spartan-6 and newer CLB architectures, where a async reset can
234 5 jdoin
    --      reduce the usability of the slice registers, due to the need to share the control 
235
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
236 7 jdoin
    --      By using GSR for the initialization, and reducing async RESET local init to the bare
237 5 jdoin
    --      essential, the model achieves better LUT/FF packing and CLB usability.
238
    --
239
    -- internal state signals for register and combinatorial stages
240
    signal state_next : natural range N+1 downto 0 := 0;
241
    signal state_reg : natural range N+1 downto 0 := 0;
242
    -- shifter signals for register and combinatorial stages
243 13 jdoin
    signal sh_next : std_logic_vector (N-1 downto 0);
244
    signal sh_reg : std_logic_vector (N-1 downto 0);
245 5 jdoin
    -- input bit sampled buffer
246
    signal rx_bit_reg : std_logic := '0';
247
    -- buffered di_i data signals for register and combinatorial stages
248 13 jdoin
    signal di_reg : std_logic_vector (N-1 downto 0);
249 5 jdoin
    -- internal wren_i stretcher for fsm combinatorial stage
250 13 jdoin
    signal wren : std_logic;
251 12 jdoin
    signal wr_ack_next : std_logic := '0';
252
    signal wr_ack_reg : std_logic := '0';
253 5 jdoin
    -- internal SSEL enable control signals
254 12 jdoin
    signal ssel_ena_next : std_logic := '0';
255
    signal ssel_ena_reg : std_logic := '0';
256 5 jdoin
    -- internal SCK enable control signals
257 12 jdoin
    signal sck_ena_next : std_logic;
258
    signal sck_ena_reg : std_logic;
259 5 jdoin
    -- buffered do_o data signals for register and combinatorial stages
260 13 jdoin
    signal do_buffer_next : std_logic_vector (N-1 downto 0);
261
    signal do_buffer_reg : std_logic_vector (N-1 downto 0);
262 5 jdoin
    -- internal signal to flag transfer to do_buffer_reg
263
    signal do_transfer_next : std_logic := '0';
264
    signal do_transfer_reg : std_logic := '0';
265
    -- internal input data request signal 
266
    signal di_req_next : std_logic := '0';
267
    signal di_req_reg : std_logic := '0';
268
    -- cross-clock do_transfer_reg -> do_valid_o_reg pipeline
269
    signal do_valid_A : std_logic := '0';
270
    signal do_valid_B : std_logic := '0';
271
    signal do_valid_C : std_logic := '0';
272
    signal do_valid_D : std_logic := '0';
273
    signal do_valid_next : std_logic := '0';
274
    signal do_valid_o_reg : std_logic := '0';
275
    -- cross-clock di_req_reg -> di_req_o_reg pipeline
276
    signal di_req_o_A : std_logic := '0';
277
    signal di_req_o_B : std_logic := '0';
278
    signal di_req_o_C : std_logic := '0';
279
    signal di_req_o_D : std_logic := '0';
280
    signal di_req_o_next : std_logic := '1';
281
    signal di_req_o_reg : std_logic := '1';
282
begin
283
    --=============================================================================================
284
    --  GENERICS CONSTRAINTS CHECKING
285
    --=============================================================================================
286
    -- minimum word width is 8 bits
287 6 jdoin
    assert N >= 8
288
    report "Generic parameter 'N' (shift register size) needs to be 8 bits minimum"
289 16 jdoin
    severity FAILURE;
290 5 jdoin
    -- minimum prefetch lookahead check
291 16 jdoin
    assert PREFETCH >= 1
292 6 jdoin
    report "Generic parameter 'PREFETCH' (lookahead count) needs to be 1 minimum"
293 16 jdoin
    severity FAILURE;
294 5 jdoin
    -- maximum prefetch lookahead check
295 6 jdoin
    assert PREFETCH <= N-5
296
    report "Generic parameter 'PREFETCH' (lookahead count) out of range, needs to be N-5 maximum"
297 16 jdoin
    severity FAILURE;
298 5 jdoin
    -- SPI_2X_CLK_DIV clock divider value must not be zero
299 6 jdoin
    assert SPI_2X_CLK_DIV > 0
300
    report "Generic parameter 'SPI_2X_CLK_DIV' must not be zero"
301 16 jdoin
    severity FAILURE;
302 5 jdoin
 
303
    --=============================================================================================
304
    --  CLOCK GENERATION
305
    --=============================================================================================
306
    -- In order to preserve global clocking resources, the core clocking scheme is completely based 
307
    -- on using clock enables to process the serial high-speed clock at lower rates for the core fsm,
308
    -- the spi clock generator and the input sampling clock.
309 22 jdoin
    -- The clock generation block derives 2 continuous antiphase signals from the 2x spi base clock 
310 5 jdoin
    -- for the core clocking.
311 14 jdoin
    -- The 2 clock phases are generated by separate and synchronous FFs, and should have only 
312 7 jdoin
    -- differential interconnect delay skew.
313 5 jdoin
    -- Clock enable signals are generated with the same phase as the 2 core clocks, and these clock 
314
    -- enables are used to control clocking of all internal synchronous circuitry. 
315
    -- The clock enable phase is selected for serial input sampling, fsm clocking, and spi SCK output, 
316
    -- based on the configuration of CPOL and CPHA.
317
    -- Each phase is selected so that all the registers can be clocked with a rising edge on all SPI
318 13 jdoin
    -- modes, by a single high-speed global clock, preserving clock resources and clock to data skew.
319 5 jdoin
    -----------------------------------------------------------------------------------------------
320 6 jdoin
    -- generate the 2x spi base clock enable from the serial high-speed input clock
321 5 jdoin
    spi_2x_ce_gen_proc: process (sclk_i) is
322
        variable clk_cnt : integer range SPI_2X_CLK_DIV-1 downto 0 := 0;
323
    begin
324
        if sclk_i'event and sclk_i = '1' then
325
            if clk_cnt = SPI_2X_CLK_DIV-1 then
326
                spi_2x_ce <= '1';
327
                clk_cnt := 0;
328
            else
329
                spi_2x_ce <= '0';
330
                clk_cnt := clk_cnt + 1;
331
            end if;
332
        end if;
333
    end process spi_2x_ce_gen_proc;
334
    -----------------------------------------------------------------------------------------------
335 6 jdoin
    -- generate the core antiphase clocks and clock enables from the 2x base CE.
336 5 jdoin
    core_clock_gen_proc : process (sclk_i) is
337
    begin
338
        if sclk_i'event and sclk_i = '1' then
339
            if spi_2x_ce = '1' then
340
                -- generate the 2 antiphase core clocks
341
                core_clk <= core_n_clk;
342
                core_n_clk <= not core_n_clk;
343
                -- generate the 2 phase core clock enables
344
                core_ce <= core_n_clk;
345
                core_n_ce <= not core_n_clk;
346
            else
347
                core_ce <= '0';
348
                core_n_ce <= '0';
349
            end if;
350
        end if;
351
    end process core_clock_gen_proc;
352 12 jdoin
 
353
    --=============================================================================================
354
    --  GENERATE BLOCKS
355
    --=============================================================================================
356 5 jdoin
    -- spi clk generator: generate spi_clk from core_clk depending on CPOL
357 12 jdoin
    spi_sck_cpol_0_proc: if CPOL = '0' generate
358
    begin
359
        spi_clk <= core_clk;            -- for CPOL=0, spi clk has idle LOW
360
    end generate;
361
 
362
    spi_sck_cpol_1_proc: if CPOL = '1' generate
363
    begin
364
        spi_clk <= core_n_clk;          -- for CPOL=1, spi clk has idle HIGH
365
    end generate;
366 5 jdoin
    -----------------------------------------------------------------------------------------------
367
    -- Sampling clock enable generation: generate 'samp_ce' from 'core_ce' or 'core_n_ce' depending on CPHA
368
    -- always sample data at the half-cycle of the fsm update cell
369 12 jdoin
    samp_ce_cpha_0_proc: if CPHA = '0' generate
370
    begin
371
        samp_ce <= core_ce;
372
    end generate;
373
 
374
    samp_ce_cpha_1_proc: if CPHA = '1' generate
375
    begin
376
        samp_ce <= core_n_ce;
377
    end generate;
378 5 jdoin
    -----------------------------------------------------------------------------------------------
379 6 jdoin
    -- FSM clock enable generation: generate 'fsm_ce' from core_ce or core_n_ce depending on CPHA
380 12 jdoin
    fsm_ce_cpha_0_proc: if CPHA = '0' generate
381
    begin
382
        fsm_ce <= core_n_ce;            -- for CPHA=0, latch registers at rising edge of negative core clock enable
383
    end generate;
384
 
385
    fsm_ce_cpha_1_proc: if CPHA = '1' generate
386
    begin
387
        fsm_ce <= core_ce;              -- for CPHA=1, latch registers at rising edge of positive core clock enable
388
    end generate;
389 13 jdoin
    -----------------------------------------------------------------------------------------------
390
    -- sck enable control: control sck advance phase for CPHA='1' relative to fsm clock
391 12 jdoin
    sck_ena_ce <= core_n_ce;            -- for CPHA=1, SCK is advanced one-half cycle
392 11 jdoin
 
393 5 jdoin
    --=============================================================================================
394
    --  REGISTERED INPUTS
395
    --=============================================================================================
396
    -- rx bit flop: capture rx bit after SAMPLE edge of sck
397 10 jdoin
    rx_bit_proc : process (sclk_i, spi_miso_i) is
398 5 jdoin
    begin
399 11 jdoin
        if sclk_i'event and sclk_i = '1' then
400
            if samp_ce = '1' then
401 5 jdoin
                rx_bit_reg <= spi_miso_i;
402 11 jdoin
            end if;
403
        end if;
404 5 jdoin
    end process rx_bit_proc;
405
 
406
    --=============================================================================================
407
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
408
    --=============================================================================================
409
    -- do_valid_o and di_req_o strobe output logic
410
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
411
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
412
    out_transfer_proc : process ( pclk_i, do_transfer_reg, di_req_reg,
413
                                  do_valid_A, do_valid_B, do_valid_D,
414
                                  di_req_o_A, di_req_o_B, di_req_o_D ) is
415
    begin
416
        if pclk_i'event and pclk_i = '1' then               -- clock at parallel port clock
417
            -- do_transfer_reg -> do_valid_o_reg
418
            do_valid_A <= do_transfer_reg;                  -- the input signal must be at least 2 clocks long
419
            do_valid_B <= do_valid_A;                       -- feed it to a ripple chain of FFDs
420
            do_valid_C <= do_valid_B;
421
            do_valid_D <= do_valid_C;
422
            do_valid_o_reg <= do_valid_next;                -- registered output pulse
423
            --------------------------------
424
            -- di_req_reg -> di_req_o_reg
425
            di_req_o_A <= di_req_reg;                       -- the input signal must be at least 2 clocks long
426
            di_req_o_B <= di_req_o_A;                       -- feed it to a ripple chain of FFDs
427
            di_req_o_C <= di_req_o_B;
428
            di_req_o_D <= di_req_o_C;
429
            di_req_o_reg <= di_req_o_next;                  -- registered output pulse
430
        end if;
431
        -- generate a 2-clocks pulse at the 3rd clock cycle
432
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
433
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
434
    end process out_transfer_proc;
435
    -- parallel load input registers: data register and write enable
436 12 jdoin
    in_transfer_proc: process ( pclk_i, wren_i, wr_ack_reg ) is
437 5 jdoin
    begin
438
        -- registered data input, input register with clock enable
439
        if pclk_i'event and pclk_i = '1' then
440
            if wren_i = '1' then
441
                di_reg <= di_i;                             -- parallel data input buffer register
442
            end if;
443
        end  if;
444
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
445
        if pclk_i'event and pclk_i = '1' then
446
            if wren_i = '1' then                            -- wren_i is the sync preset for wren
447
                wren <= '1';
448 12 jdoin
            elsif wr_ack_reg = '1' then                     -- wr_ack is the sync reset for wren
449 5 jdoin
                wren <= '0';
450
            end if;
451
        end  if;
452
    end process in_transfer_proc;
453
 
454
    --=============================================================================================
455 13 jdoin
    --  REGISTER TRANSFER PROCESSES
456 7 jdoin
    --=============================================================================================
457
    -- fsm state and data registers: synchronous to the spi base reference clock
458
    core_reg_proc : process (sclk_i) is
459
    begin
460
        -- FF registers clocked on rising edge and cleared on sync rst_i
461
        if sclk_i'event and sclk_i = '1' then
462
            if rst_i = '1' then                             -- sync reset
463
                state_reg <= 0;                             -- only provide local reset for the state machine
464
            elsif fsm_ce = '1' then                         -- fsm_ce is clock enable for the fsm
465
                state_reg <= state_next;                    -- state register
466
            end if;
467
        end if;
468 11 jdoin
        -- FF registers clocked synchronous to the fsm state
469 7 jdoin
        if sclk_i'event and sclk_i = '1' then
470
            if fsm_ce = '1' then
471
                sh_reg <= sh_next;                          -- shift register
472 12 jdoin
                ssel_ena_reg <= ssel_ena_next;              -- spi select enable
473 7 jdoin
                do_buffer_reg <= do_buffer_next;            -- registered output data buffer 
474
                do_transfer_reg <= do_transfer_next;        -- output data transferred to buffer
475
                di_req_reg <= di_req_next;                  -- input data request
476 12 jdoin
                wr_ack_reg <= wr_ack_next;                  -- write acknowledge for data load synchronization
477 7 jdoin
            end if;
478
        end if;
479 11 jdoin
        -- FF registers clocked one-half cycle earlier than the fsm state
480 12 jdoin
        if sclk_i'event and sclk_i = '1' then
481
            if sck_ena_ce = '1' then
482
                sck_ena_reg <= sck_ena_next;                -- spi clock enable: look ahead logic
483
            end if;
484
        end if;
485 7 jdoin
    end process core_reg_proc;
486
 
487
    --=============================================================================================
488 13 jdoin
    --  COMBINATORIAL LOGIC PROCESSES
489 5 jdoin
    --=============================================================================================
490
    -- state and datapath combinatorial logic
491 12 jdoin
    core_combi_proc : process ( sh_reg, state_reg, rx_bit_reg, ssel_ena_reg, sck_ena_reg, do_buffer_reg,
492
                                do_transfer_reg, wr_ack_reg, di_req_reg, di_reg, wren ) is
493 5 jdoin
    begin
494
        sh_next <= sh_reg;                                              -- all output signals are assigned to (avoid latches)
495 12 jdoin
        ssel_ena_next <= ssel_ena_reg;                                  -- controls the slave select line
496
        sck_ena_next <= sck_ena_reg;                                    -- controls the clock enable of spi sck line
497 5 jdoin
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
498
        do_transfer_next <= do_transfer_reg;                            -- output data flag
499 12 jdoin
        wr_ack_next <= wr_ack_reg;                                      -- write acknowledge
500
        di_req_next <= di_req_reg;                                      -- prefetch data request
501 13 jdoin
        spi_mosi_o <= sh_reg(N-1);                                      -- default to avoid latch inference
502 12 jdoin
        state_next <= state_reg;                                        -- next state 
503 5 jdoin
        case state_reg is
504 16 jdoin
 
505 5 jdoin
            when (N+1) =>                                               -- this state is to enable SSEL before SCK
506 13 jdoin
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
507 12 jdoin
                ssel_ena_next <= '1';                                   -- tx in progress: will assert SSEL
508
                sck_ena_next <= '1';                                    -- enable SCK on next cycle (stays off on first SSEL clock cycle)
509
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
510
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
511
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
512 16 jdoin
 
513
            when (N) =>                                                 -- deassert 'di_rdy' and stretch do_valid
514 13 jdoin
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
515 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
516 5 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
517
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
518 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
519
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
520 16 jdoin
 
521
            when (N-1) downto (PREFETCH+3) =>                           -- remove 'do_transfer' and shift bits
522 13 jdoin
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
523 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
524 16 jdoin
                do_transfer_next <= '0';                                -- reset 'do_valid' transfer signal
525 5 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
526
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
527 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
528
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
529 16 jdoin
 
530
            when (PREFETCH+2) downto 2 =>                               -- raise prefetch 'di_req_o' signal
531 13 jdoin
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
532 5 jdoin
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
533
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
534
                sh_next(0) <= rx_bit_reg;                               -- shift in rx bit into LSb
535 12 jdoin
                wr_ack_next <= '0';                                     -- remove write acknowledge for all but the load stages
536
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
537 16 jdoin
 
538
            when 1 =>                                                   -- transfer rx data to do_buffer and restart if new data is written
539 13 jdoin
                spi_mosi_o <= sh_reg(N-1);                              -- shift out tx bit from the MSb
540 5 jdoin
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
541
                do_buffer_next(N-1 downto 1) <= sh_reg(N-2 downto 0);   -- shift rx data directly into rx buffer
542
                do_buffer_next(0) <= rx_bit_reg;                        -- shift last rx bit into rx buffer
543
                do_transfer_next <= '1';                                -- signal transfer to do_buffer
544
                if wren = '1' then                                      -- load tx register if valid data present at di_i
545
                    state_next <= N;                                    -- next state is top bit of new data
546
                    sh_next <= di_reg;                                  -- load parallel data from di_reg into shifter
547 12 jdoin
                    sck_ena_next <= '1';                                -- SCK enabled
548
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
549 5 jdoin
                else
550 12 jdoin
                    sck_ena_next <= '0';                                -- SCK disabled: tx empty, no data to send
551
                    wr_ack_next <= '0';                                 -- remove write acknowledge for all but the load stages
552
                    state_next <= state_reg - 1;                        -- update next state at each sck pulse
553 5 jdoin
                end if;
554 16 jdoin
 
555
            when 0 =>                                                   -- idle state: start and end of transmission
556 5 jdoin
                di_req_next <= '1';                                     -- will request data if shifter empty
557 12 jdoin
                sck_ena_next <= '0';                                    -- SCK disabled: tx empty, no data to send
558 5 jdoin
                if wren = '1' then                                      -- load tx register if valid data present at di_i
559 13 jdoin
                    spi_mosi_o <= di_reg(N-1);                          -- special case: shift out first tx bit from the MSb (look ahead)
560 12 jdoin
                    ssel_ena_next <= '1';                               -- enable interface SSEL
561 5 jdoin
                    state_next <= N+1;                                  -- start from idle: let one cycle for SSEL settling
562
                    sh_next <= di_reg;                                  -- load bits from di_reg into shifter
563 12 jdoin
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
564 5 jdoin
                else
565 13 jdoin
                    spi_mosi_o <= sh_reg(N-1);                          -- shift out tx bit from the MSb
566 12 jdoin
                    ssel_ena_next <= '0';                               -- deassert SSEL: interface is idle
567
                    wr_ack_next <= '0';                                 -- remove write acknowledge for all but the load stages
568 5 jdoin
                    state_next <= 0;                                    -- when idle, keep this state
569
                end if;
570 16 jdoin
 
571 5 jdoin
            when others =>
572
                state_next <= 0;                                        -- state 0 is safe state
573
        end case;
574
    end process core_combi_proc;
575
 
576
    --=============================================================================================
577
    --  OUTPUT LOGIC PROCESSES
578
    --=============================================================================================
579
    -- data output processes
580 12 jdoin
    spi_ssel_o_proc:    spi_ssel_o <= not ssel_ena_reg;                 -- active-low slave select line 
581
    do_o_proc:          do_o <= do_buffer_reg;                          -- parallel data out
582
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                   -- data out valid
583
    di_req_o_proc:      di_req_o <= di_req_o_reg;                       -- input data request for next cycle
584
    wr_ack_o_proc:      wr_ack_o <= wr_ack_reg;                         -- write acknowledge
585 5 jdoin
    -----------------------------------------------------------------------------------------------
586
    -- SCK out logic: pipeline phase compensation for the SCK line
587
    -----------------------------------------------------------------------------------------------
588 12 jdoin
    -- This is a MUX with an output register. 
589
    -- The register gives us a pipeline delay for the SCK line, pairing with the state machine moore 
590
    -- output pipeline delay for the MOSI line, and thus enabling higher SCK frequency. 
591
    spi_sck_o_gen_proc : process (sclk_i, sck_ena_reg, spi_clk, spi_clk_reg) is
592 5 jdoin
    begin
593 12 jdoin
        if sclk_i'event and sclk_i = '1' then
594
            if sck_ena_reg = '1' then
595 5 jdoin
                spi_clk_reg <= spi_clk;                                 -- copy the selected clock polarity
596 12 jdoin
            else
597
                spi_clk_reg <= CPOL;                                    -- when clock disabled, set to idle polarity
598 5 jdoin
            end if;
599
        end if;
600
        spi_sck_o <= spi_clk_reg;                                       -- connect register to output
601
    end process spi_sck_o_gen_proc;
602
 
603
    --=============================================================================================
604
    --  DEBUG LOGIC PROCESSES
605
    --=============================================================================================
606 13 jdoin
    -- these signals are useful for verification, and can be deleted after debug.
607 5 jdoin
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
608 13 jdoin
    state_dbg_proc:     state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4));
609 5 jdoin
    rx_bit_reg_proc:    rx_bit_reg_o <= rx_bit_reg;
610
    wren_o_proc:        wren_o <= wren;
611 12 jdoin
    sh_reg_dbg_proc:    sh_reg_dbg_o <= sh_reg;
612 5 jdoin
    core_clk_o_proc:    core_clk_o <= core_clk;
613
    core_n_clk_o_proc:  core_n_clk_o <= core_n_clk;
614
    core_ce_o_proc:     core_ce_o <= core_ce;
615
    core_n_ce_o_proc:   core_n_ce_o <= core_n_ce;
616 12 jdoin
    sck_ena_o_proc:     sck_ena_o <= sck_ena_reg;
617
    sck_ena_ce_o_proc:  sck_ena_ce_o <= sck_ena_ce;
618 5 jdoin
 
619 13 jdoin
end architecture rtl;
620 5 jdoin
 

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