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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_test.vhd] - Blame information for rev 12

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1 12 jdoin
-- TestBench Template 
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity testbench is
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end testbench;
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architecture behavior of testbench is
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    --=============================================================================================
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    -- Constants
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    --=============================================================================================
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    -- clock period
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    constant CLK_PERIOD : time := 10 ns;
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    -- button definitions
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    constant btRESET    : integer := 0;             -- these are constants to use as btn_i(x)
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    constant btUP       : integer := 1;
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    constant btLEFT     : integer := 2;
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    constant btDOWN     : integer := 3;
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    constant btRIGHT    : integer := 4;
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    constant btCENTER   : integer := 5;
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    --=============================================================================================
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    -- COMPONENT DECLARATIONS
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    --=============================================================================================
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    component spi_master_atlys_top
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    port(
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        gclk_i : in std_logic;
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        sw_i : in std_logic_vector(7 downto 0);
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        btn_i : in std_logic_vector(5 downto 0);
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        spi_ssel_o : out std_logic;
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        spi_sck_o : out std_logic;
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        spi_mosi_o : out std_logic;
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        spi_miso_o : out std_logic;
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        led_o : out std_logic_vector(7 downto 0);
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        dbg_o : out std_logic_vector(11 downto 0)
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    );
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    end component;
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    --=============================================================================================
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    -- Signals for state machine control
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    --=============================================================================================
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    --=============================================================================================
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    -- Signals for internal operation
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    --=============================================================================================
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    --- clock signals ---
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    signal sysclk           : std_logic := '0';                                 -- 100MHz clock
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    --- switch debouncer signals ---
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    signal sw_data          : std_logic_vector (7 downto 0) := (others => '0'); -- switch data
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    --- pushbutton debouncer signals ---
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    signal btn_data         : std_logic_vector (5 downto 0) := (others => '0'); -- pushbuttons
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    --- spi port signals ---
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    signal spi_ssel         : std_logic;
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    signal spi_sck          : std_logic;
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    signal spi_mosi         : std_logic;
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    signal spi_miso         : std_logic;
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    -- debug output signals
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    signal leds             : std_logic_vector (7 downto 0) := (others => '0');
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    signal dbg              : std_logic_vector (11 downto 0) := (others => '0');
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    -- debug ports
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    signal spi_do_s         : std_logic_vector (7 downto 0) := (others => '0');
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    signal spi_state_s      : std_logic_vector (3 downto 0) := (others => '0');
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begin
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    --=============================================================================================
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    -- COMPONENT INSTANTIATIONS FOR THE CORES UNDER TEST
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    --=============================================================================================
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    -- spi_master_atlys_top:
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    --      receives the 100 MHz clock from the board clock oscillator
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    --      receives the 8 slide switches and 5 pushbuttons as test stimuli
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    --      connects to 4 spi signals
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    --      connects to 8 board LEDs
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    --      connects to 12 debug pins
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        inst_spi_master_atlys_top: spi_master_atlys_top
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    port map(
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        gclk_i => sysclk,
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        spi_ssel_o => spi_ssel,
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        spi_sck_o => spi_sck,
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        spi_mosi_o => spi_mosi,
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        spi_miso_o => spi_miso,
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        sw_i => sw_data,
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        btn_i => btn_data,
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        led_o => leds,
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        dbg_o => dbg
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        );
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    spi_do_s <= dbg(7 downto 0);
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    spi_state_s <= dbg(11 downto 8);
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    --=============================================================================================
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    -- CLOCK GENERATION
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    --=============================================================================================
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    gclk_proc: process is
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    begin
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        loop
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            sysclk <= not sysclk;
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            wait for CLK_PERIOD / 2;
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        end loop;
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    end process gclk_proc;
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    --=============================================================================================
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    -- TEST BENCH STIMULI
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    --=============================================================================================
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    tb : process
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    begin
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        wait for 100 ns; -- wait until global set/reset completes
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        sw_data <= X"5A";
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        btn_data(btRIGHT) <= '1';
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        wait; -- will wait forever
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    end process tb;
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    --  End Test Bench 
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END;

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