OpenCores
URL https://opencores.org/ocsvn/spi_master_slave/spi_master_slave/trunk

Subversion Repositories spi_master_slave

[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top.syr] - Blame information for rev 22

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Line No. Rev Author Line
1 20 jdoin
Release 13.1 - xst O.40d (nt)
2
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
3
--> Parameter TMPDIR set to xst/projnav.tmp
4
 
5
 
6 22 jdoin
Total REAL time to Xst completion: 0.00 secs
7
Total CPU time to Xst completion: 0.08 secs
8 20 jdoin
 
9
--> Parameter xsthdpdir set to xst
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11
 
12 22 jdoin
Total REAL time to Xst completion: 0.00 secs
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Total CPU time to Xst completion: 0.08 secs
14 20 jdoin
 
15
--> Reading design: spi_master_atlys_top.prj
16
 
17
TABLE OF CONTENTS
18
  1) Synthesis Options Summary
19
  2) HDL Parsing
20
  3) HDL Elaboration
21
  4) HDL Synthesis
22
       4.1) HDL Synthesis Report
23
  5) Advanced HDL Synthesis
24
       5.1) Advanced HDL Synthesis Report
25
  6) Low Level Synthesis
26
  7) Partition Report
27
  8) Design Summary
28
       8.1) Primitive and Black Box Usage
29
       8.2) Device utilization summary
30
       8.3) Partition Resource Summary
31
       8.4) Timing Report
32
            8.4.1) Clock Information
33
            8.4.2) Asynchronous Control Signals Information
34
            8.4.3) Timing Summary
35
            8.4.4) Timing Details
36
            8.4.5) Cross Clock Domains Report
37
 
38
 
39
=========================================================================
40
*                      Synthesis Options Summary                        *
41
=========================================================================
42
---- Source Parameters
43
Input File Name                    : "spi_master_atlys_top.prj"
44
Input Format                       : mixed
45
Ignore Synthesis Constraint File   : NO
46
 
47
---- Target Parameters
48
Output File Name                   : "spi_master_atlys_top"
49
Output Format                      : NGC
50
Target Device                      : xc6slx45-2-csg324
51
 
52
---- Source Options
53
Top Module Name                    : spi_master_atlys_top
54
Automatic FSM Extraction           : YES
55
FSM Encoding Algorithm             : Gray
56
Safe Implementation                : No
57
FSM Style                          : LUT
58
RAM Extraction                     : No
59
ROM Extraction                     : No
60
Shift Register Extraction          : NO
61
Resource Sharing                   : YES
62
Asynchronous To Synchronous        : NO
63
Shift Register Minimum Size        : 2
64
Use DSP Block                      : Auto
65
Automatic Register Balancing       : No
66
 
67
---- Target Options
68
LUT Combining                      : Area
69
Reduce Control Sets                : Auto
70
Add IO Buffers                     : YES
71
Global Maximum Fanout              : 100000
72
Add Generic Clock Buffer(BUFG)     : 16
73
Register Duplication               : YES
74
Optimize Instantiated Primitives   : NO
75
Use Clock Enable                   : Auto
76
Use Synchronous Set                : Auto
77
Use Synchronous Reset              : Auto
78
Pack IO Registers into IOBs        : Auto
79
Equivalent register Removal        : YES
80
 
81
---- General Options
82
Optimization Goal                  : Speed
83
Optimization Effort                : 2
84
Power Reduction                    : NO
85
Keep Hierarchy                     : No
86
Netlist Hierarchy                  : As_Optimized
87
RTL Output                         : Yes
88
Global Optimization                : AllClockNets
89
Read Cores                         : YES
90
Write Timing Constraints           : NO
91
Cross Clock Analysis               : NO
92
Hierarchy Separator                : /
93
Bus Delimiter                      : <>
94
Case Specifier                     : Maintain
95
Slice Utilization Ratio            : 100
96
BRAM Utilization Ratio             : 100
97
DSP48 Utilization Ratio            : 100
98
Auto BRAM Packing                  : NO
99
Slice Utilization Ratio Delta      : 5
100
 
101
=========================================================================
102
 
103
 
104
=========================================================================
105
*                          HDL Parsing                                  *
106
=========================================================================
107 22 jdoin
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" into library work
108 20 jdoin
Parsing entity .
109
Parsing architecture  of entity .
110 22 jdoin
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 361: Case choice must be a locally static expression
111
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 369: Case choice must be a locally static expression
112
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_slave.vhd" Line 378: Case choice must be a locally static expression
113
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" into library work
114 20 jdoin
Parsing entity .
115
Parsing architecture  of entity .
116 22 jdoin
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 505: Case choice must be a locally static expression
117
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 513: Case choice must be a locally static expression
118
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 521: Case choice must be a locally static expression
119
WARNING:HDLCompiler:957 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master.vhd" Line 530: Case choice must be a locally static expression
120
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\grp_debouncer.vhd" into library work
121 20 jdoin
Parsing entity .
122
Parsing architecture  of entity .
123 22 jdoin
Parsing VHDL file "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" into library work
124 20 jdoin
Parsing entity .
125 22 jdoin
Parsing architecture  of entity .
126 20 jdoin
 
127
=========================================================================
128
*                            HDL Elaboration                            *
129
=========================================================================
130
 
131 22 jdoin
Elaborating entity  (architecture ) with generics from library .
132 20 jdoin
 
133
Elaborating entity  (architecture ) with generics from library .
134
 
135
Elaborating entity  (architecture ) with generics from library .
136
 
137
Elaborating entity  (architecture ) with generics from library .
138
 
139
Elaborating entity  (architecture ) with generics from library .
140 22 jdoin
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 459. Case statement is complete. others clause is never selected
141
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 521. Case statement is complete. others clause is never selected
142
INFO:HDLCompiler:679 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\spimasterslave\spi_master_slave\trunk\syn\spi_master_atlys_top.vhd" Line 571. Case statement is complete. others clause is never selected
143 20 jdoin
 
144
=========================================================================
145
*                           HDL Synthesis                               *
146
=========================================================================
147
 
148
Synthesizing Unit .
149 22 jdoin
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd".
150
        N = 8
151
        CPOL = '0'
152
        CPHA = '0'
153
        PREFETCH = 3
154
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
155
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
156
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
157
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
158
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
159
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
160
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
161
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
162
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
163
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 184: Output port  of the instance  is unconnected or connected to loadless signal.
164
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
165
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
166
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
167
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 205: Output port  of the instance  is unconnected or connected to loadless signal.
168
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 224: Output port  of the instance  is unconnected or connected to loadless signal.
169
INFO:Xst:3210 - "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master_atlys_top.vhd" line 233: Output port  of the instance  is unconnected or connected to loadless signal.
170 20 jdoin
    Found 1-bit register for signal .
171
    Found 1-bit register for signal .
172
    Found 1-bit register for signal .
173
    Found 1-bit register for signal .
174
    Found 8-bit register for signal .
175
    Found 4-bit register for signal .
176
    Found 3-bit register for signal .
177
    Found 3-bit register for signal .
178
    Found 1-bit register for signal .
179
    Found 8-bit register for signal .
180
    Found 1-bit register for signal .
181
    Found 1-bit register for signal .
182
    Found 8-bit register for signal .
183
    Found 6-bit register for signal .
184
    Found 1-bit register for signal .
185
    Found 8-bit register for signal .
186
    Found 8-bit register for signal .
187
    Found 8-bit register for signal .
188
    Found 8-bit register for signal .
189
    Found 1-bit register for signal .
190
    Found finite state machine  for signal .
191
    -----------------------------------------------------------------------
192
    | States             | 7                                              |
193
    | Transitions        | 20                                             |
194
    | Inputs             | 2                                              |
195
    | Outputs            | 3                                              |
196
    | Clock              | gclk_i (rising_edge)                           |
197
    | Reset              | spi_ssel_o (positive)                          |
198
    | Reset type         | synchronous                                    |
199
    | Reset State        | st_reset                                       |
200
    | Power Up State     | st_reset                                       |
201
    | Encoding           | Gray                                           |
202
    | Implementation     | LUT                                            |
203
    -----------------------------------------------------------------------
204
    Found finite state machine  for signal .
205
    -----------------------------------------------------------------------
206
    | States             | 11                                             |
207
    | Transitions        | 36                                             |
208
    | Inputs             | 11                                             |
209
    | Outputs            | 10                                             |
210
    | Clock              | gclk_i (rising_edge)                           |
211
    | Reset              | clear (positive)                               |
212
    | Reset type         | synchronous                                    |
213
    | Reset State        | st_reset                                       |
214
    | Power Up State     | st_reset                                       |
215
    | Encoding           | Gray                                           |
216
    | Implementation     | LUT                                            |
217
    -----------------------------------------------------------------------
218
INFO:Xst:1799 - State st_wait_spi_ack_2 is never reached in FSM .
219
    Found finite state machine  for signal .
220
    -----------------------------------------------------------------------
221
    | States             | 8                                              |
222
    | Transitions        | 20                                             |
223
    | Inputs             | 5                                              |
224
    | Outputs            | 9                                              |
225
    | Clock              | gclk_i (rising_edge)                           |
226
    | Reset              | spi_ssel_o (positive)                          |
227
    | Reset type         | synchronous                                    |
228
    | Reset State        | st_reset                                       |
229
    | Power Up State     | st_reset                                       |
230
    | Encoding           | Gray                                           |
231
    | Implementation     | LUT                                            |
232
    -----------------------------------------------------------------------
233 22 jdoin
    Found 1-bit adder for signal > created at line 276.
234
    Found 1-bit adder for signal > created at line 290.
235
    Found 8-bit comparator equal for signal <_n0380> created at line 362
236
    Found 6-bit comparator equal for signal <_n0400> created at line 365
237 20 jdoin
    Summary:
238
        inferred   2 Adder/Subtractor(s).
239
        inferred  71 D-type flip-flop(s).
240
        inferred   2 Comparator(s).
241
        inferred   5 Multiplexer(s).
242
        inferred   3 Finite State Machine(s).
243
Unit  synthesized.
244
 
245
Synthesizing Unit .
246 22 jdoin
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_master.vhd".
247 20 jdoin
        N = 8
248
        CPOL = '0'
249
        CPHA = '0'
250
        PREFETCH = 3
251
        SPI_2X_CLK_DIV = 1
252
    Found 1-bit register for signal .
253
    Found 1-bit register for signal .
254
    Found 1-bit register for signal .
255
    Found 1-bit register for signal .
256
    Found 1-bit register for signal .
257
    Found 1-bit register for signal .
258
    Found 1-bit register for signal .
259
    Found 1-bit register for signal .
260
    Found 1-bit register for signal .
261
    Found 1-bit register for signal .
262
    Found 1-bit register for signal .
263
    Found 1-bit register for signal .
264
    Found 1-bit register for signal .
265
    Found 1-bit register for signal .
266
    Found 1-bit register for signal .
267
    Found 1-bit register for signal .
268
    Found 8-bit register for signal .
269
    Found 1-bit register for signal .
270
    Found 4-bit register for signal .
271
    Found 8-bit register for signal .
272
    Found 1-bit register for signal .
273
    Found 8-bit register for signal .
274
    Found 1-bit register for signal .
275
    Found 1-bit register for signal .
276
    Found 1-bit register for signal .
277
    Found 1-bit register for signal .
278
    Found 1-bit register for signal .
279
    Found 1-bit register for signal .
280 22 jdoin
    Found 1-bit adder for signal > created at line 330.
281
    Found 4-bit subtractor for signal > created at line 528.
282
    Found 4-bit comparator greater for signal  created at line 521
283
    Found 4-bit comparator greater for signal  created at line 521
284
    Found 4-bit comparator greater for signal  created at line 530
285
    Found 4-bit comparator greater for signal  created at line 530
286 20 jdoin
    Summary:
287
        inferred   2 Adder/Subtractor(s).
288
        inferred  52 D-type flip-flop(s).
289
        inferred   4 Comparator(s).
290
        inferred  13 Multiplexer(s).
291
Unit  synthesized.
292
 
293
Synthesizing Unit .
294 22 jdoin
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/spi_slave.vhd".
295 20 jdoin
        N = 8
296
        CPOL = '0'
297
        CPHA = '0'
298
        PREFETCH = 3
299 22 jdoin
    Found 1-bit register for signal .
300 20 jdoin
    Found 4-bit register for signal .
301
    Found 1-bit register for signal .
302
    Found 1-bit register for signal .
303
    Found 1-bit register for signal .
304
    Found 1-bit register for signal .
305
    Found 1-bit register for signal .
306
    Found 1-bit register for signal .
307
    Found 1-bit register for signal .
308
    Found 1-bit register for signal .
309
    Found 1-bit register for signal .
310
    Found 8-bit register for signal .
311
    Found 1-bit register for signal .
312
    Found 8-bit register for signal .
313
    Found 8-bit register for signal .
314
    Found 1-bit register for signal .
315
    Found 1-bit register for signal .
316
    Found 1-bit register for signal .
317
    Found 1-bit register for signal .
318
    Found 1-bit register for signal .
319 22 jdoin
    Found 4-bit subtractor for signal > created at line 376.
320
    Found 4-bit comparator greater for signal  created at line 369
321
    Found 4-bit comparator greater for signal  created at line 369
322
    Found 4-bit comparator greater for signal  created at line 378
323
    Found 4-bit comparator greater for signal  created at line 378
324 20 jdoin
    Summary:
325
        inferred   1 Adder/Subtractor(s).
326 22 jdoin
        inferred  44 D-type flip-flop(s).
327 20 jdoin
        inferred   4 Comparator(s).
328
        inferred  22 Multiplexer(s).
329
Unit  synthesized.
330
 
331
Synthesizing Unit .
332 22 jdoin
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
333 20 jdoin
        N = 8
334 22 jdoin
        CNT_VAL = 20000
335 20 jdoin
    Found 8-bit register for signal .
336
    Found 8-bit register for signal .
337
    Found 8-bit register for signal .
338 22 jdoin
    Found 15-bit register for signal .
339
    Found 16-bit adder for signal  created at line 162.
340 20 jdoin
    Found 8-bit comparator not equal for signal  created at line 184
341
    Found 8-bit comparator not equal for signal  created at line 190
342
    Summary:
343
        inferred   1 Adder/Subtractor(s).
344 22 jdoin
        inferred  39 D-type flip-flop(s).
345 20 jdoin
        inferred   2 Comparator(s).
346
Unit  synthesized.
347
 
348
Synthesizing Unit .
349 22 jdoin
    Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/spimasterslave/spi_master_slave/trunk/syn/grp_debouncer.vhd".
350 20 jdoin
        N = 6
351 22 jdoin
        CNT_VAL = 20000
352 20 jdoin
    Found 6-bit register for signal .
353
    Found 6-bit register for signal .
354
    Found 6-bit register for signal .
355 22 jdoin
    Found 15-bit register for signal .
356
    Found 16-bit adder for signal  created at line 162.
357 20 jdoin
    Found 6-bit comparator not equal for signal  created at line 184
358
    Found 6-bit comparator not equal for signal  created at line 190
359
    Summary:
360
        inferred   1 Adder/Subtractor(s).
361 22 jdoin
        inferred  33 D-type flip-flop(s).
362 20 jdoin
        inferred   2 Comparator(s).
363
Unit  synthesized.
364
 
365
=========================================================================
366
HDL Synthesis Report
367
 
368
Macro Statistics
369
# Adders/Subtractors                                   : 7
370
 1-bit adder                                           : 3
371 22 jdoin
 16-bit adder                                          : 2
372 20 jdoin
 4-bit subtractor                                      : 2
373 22 jdoin
# Registers                                            : 73
374
 1-bit register                                        : 49
375
 15-bit register                                       : 2
376 20 jdoin
 4-bit register                                        : 2
377
 6-bit register                                        : 4
378 22 jdoin
 8-bit register                                        : 16
379 20 jdoin
# Comparators                                          : 14
380
 4-bit comparator greater                              : 8
381
 6-bit comparator equal                                : 1
382
 6-bit comparator not equal                            : 2
383
 8-bit comparator equal                                : 1
384
 8-bit comparator not equal                            : 2
385
# Multiplexers                                         : 40
386
 1-bit 2-to-1 multiplexer                              : 13
387
 4-bit 2-to-1 multiplexer                              : 12
388
 8-bit 2-to-1 multiplexer                              : 15
389
# FSMs                                                 : 3
390
 
391
=========================================================================
392
 
393
=========================================================================
394
*                       Advanced HDL Synthesis                          *
395
=========================================================================
396
 
397
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
398
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
399
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
400
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
401
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
402
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
403
 
404
Synthesizing (advanced) Unit .
405
The following registers are absorbed into counter : 1 register on signal .
406
Unit  synthesized (advanced).
407
 
408
Synthesizing (advanced) Unit .
409
The following registers are absorbed into counter : 1 register on signal .
410
Unit  synthesized (advanced).
411
 
412
Synthesizing (advanced) Unit .
413
The following registers are absorbed into counter : 1 register on signal .
414
Unit  synthesized (advanced).
415
 
416
Synthesizing (advanced) Unit .
417
The following registers are absorbed into counter : 1 register on signal .
418
The following registers are absorbed into counter : 1 register on signal .
419
Unit  synthesized (advanced).
420
 
421
=========================================================================
422
Advanced HDL Synthesis Report
423
 
424
Macro Statistics
425
# Adders/Subtractors                                   : 2
426
 4-bit subtractor                                      : 2
427
# Counters                                             : 5
428
 1-bit up counter                                      : 3
429 22 jdoin
 15-bit up counter                                     : 2
430
# Registers                                            : 206
431
 Flip-Flops                                            : 206
432 20 jdoin
# Comparators                                          : 14
433
 4-bit comparator greater                              : 8
434
 6-bit comparator equal                                : 1
435
 6-bit comparator not equal                            : 2
436
 8-bit comparator equal                                : 1
437
 8-bit comparator not equal                            : 2
438 22 jdoin
# Multiplexers                                         : 47
439
 1-bit 2-to-1 multiplexer                              : 21
440 20 jdoin
 4-bit 2-to-1 multiplexer                              : 12
441
 8-bit 2-to-1 multiplexer                              : 14
442
# FSMs                                                 : 3
443
 
444
=========================================================================
445
 
446
=========================================================================
447
*                         Low Level Synthesis                           *
448
=========================================================================
449
WARNING:Xst:1293 - FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
450
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
451
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
452
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
453
WARNING:Xst:1710 - FF/Latch  (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
454
Optimizing FSM  on signal  with Gray encoding.
455
--------------------------------------
456
 State                    | Encoding
457
--------------------------------------
458
 st_reset                 | 000
459
 st_wait_spi_do_valid_1   | 001
460
 st_wait_spi_n_do_valid_1 | 011
461
 st_wait_spi_do_valid_2   | 010
462
 st_wait_spi_n_do_valid_2 | 110
463
 st_wait_spi_do_valid_3   | 111
464
 st_wait_spi_n_do_valid_3 | 101
465
--------------------------------------
466
Optimizing FSM  on signal  with Gray encoding.
467
----------------------------------
468
 State                | Encoding
469
----------------------------------
470
 st_reset             | 0000
471
 st_wait_spi_idle     | 0001
472
 st_wait_new_switch   | 0011
473
 st_send_spi_data_sw  | 0110
474
 st_wait_spi_ack_sw   | 0111
475
 st_send_spi_data_1   | 0010
476
 st_wait_spi_ack_1    | 0100
477
 st_wait_spi_di_req_2 | 0101
478
 st_wait_spi_ack_2    | 1100
479
 st_wait_spi_di_req_3 | 1101
480
 st_wait_spi_ack_3    | 1111
481
----------------------------------
482
Optimizing FSM  on signal  with Gray encoding.
483
------------------------------------
484
 State                  | Encoding
485
------------------------------------
486
 st_reset               | 000
487
 st_wait_spi_start      | 001
488
 st_wait_spi_di_req_2   | 011
489
 st_wait_spi_ack_2      | unreached
490
 st_wait_spi_do_valid_1 | 010
491
 st_wait_spi_di_req_3   | 110
492
 st_wait_spi_ack_3      | 111
493
 st_wait_spi_end        | 101
494
------------------------------------
495
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_6 hinder the constant cleaning in the block spi_master_atlys_top.
496
   You should achieve better results by setting this init to 1.
497
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_4 hinder the constant cleaning in the block spi_master_atlys_top.
498
   You should achieve better results by setting this init to 1.
499
WARNING:Xst:1426 - The value init of the FF/Latch spi_di_reg_s_0 hinder the constant cleaning in the block spi_master_atlys_top.
500
   You should achieve better results by setting this init to 1.
501 22 jdoin
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
502
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
503 20 jdoin
 
504
Optimizing unit  ...
505
 
506
Optimizing unit  ...
507
 
508
Optimizing unit  ...
509
 
510
Optimizing unit  ...
511
 
512
Optimizing unit  ...
513
WARNING:Xst:1293 - FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
514
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
515
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
516
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
517
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.
518
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  has a constant value of 1 in block . This FF/Latch will be trimmed during the optimization process.
519 22 jdoin
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following 2 FFs/Latches, which will be removed :  
520
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
521 20 jdoin
INFO:Xst:2261 - The FF/Latch  in Unit  is equivalent to the following FF/Latch, which will be removed : 
522
INFO:Xst:3203 - The FF/Latch  in Unit  is the opposite to the following 2 FFs/Latches, which will be removed :  
523
 
524
Mapping all equations...
525
Building and optimizing final netlist ...
526
Found area constraint ratio of 100 (+ 5) on block spi_master_atlys_top, actual ratio is 1.
527
FlipFlop Inst_spi_slave_port/state_reg_0 has been replicated 1 time(s)
528
FlipFlop Inst_spi_slave_port/state_reg_1 has been replicated 1 time(s)
529
FlipFlop Inst_spi_slave_port/state_reg_2 has been replicated 2 time(s)
530
 
531
Final Macro Processing ...
532
 
533
=========================================================================
534
Final Register Report
535
 
536
Macro Statistics
537 22 jdoin
# Registers                                            : 232
538
 Flip-Flops                                            : 232
539 20 jdoin
 
540
=========================================================================
541
 
542
=========================================================================
543
*                           Partition Report                            *
544
=========================================================================
545
 
546
Partition Implementation Status
547
-------------------------------
548
 
549
  No Partitions were found in this design.
550
 
551
-------------------------------
552
 
553
=========================================================================
554
*                            Design Summary                             *
555
=========================================================================
556
 
557
Top Level Output File Name         : spi_master_atlys_top.ngc
558
 
559
Primitive and Black Box Usage:
560
------------------------------
561 22 jdoin
# BELS                             : 259
562 20 jdoin
#      GND                         : 1
563
#      INV                         : 4
564 22 jdoin
#      LUT1                        : 28
565
#      LUT2                        : 3
566
#      LUT3                        : 26
567 20 jdoin
#      LUT4                        : 17
568 22 jdoin
#      LUT5                        : 62
569
#      LUT6                        : 55
570
#      MUXCY                       : 28
571 20 jdoin
#      MUXF7                       : 4
572
#      VCC                         : 1
573 22 jdoin
#      XORCY                       : 30
574
# FlipFlops/Latches                : 232
575
#      FD                          : 97
576 20 jdoin
#      FD_1                        : 1
577
#      FDC                         : 8
578
#      FDE                         : 111
579 22 jdoin
#      FDP_1                       : 1
580 20 jdoin
#      FDR                         : 10
581
#      FDRE                        : 4
582
# Clock Buffers                    : 2
583
#      BUFG                        : 1
584
#      BUFGP                       : 1
585
# IO Buffers                       : 62
586
#      IBUF                        : 14
587
#      OBUF                        : 48
588
 
589
Device utilization summary:
590
---------------------------
591
 
592
Selected Device : 6slx45csg324-2
593
 
594
 
595
Slice Logic Utilization:
596 22 jdoin
 Number of Slice Registers:             232  out of  54576     0%
597
 Number of Slice LUTs:                  195  out of  27288     0%
598
    Number used as Logic:               195  out of  27288     0%
599 20 jdoin
 
600
Slice Logic Distribution:
601 22 jdoin
 Number of LUT Flip Flop pairs used:    301
602
   Number with an unused Flip Flop:      69  out of    301    22%
603
   Number with an unused LUT:           106  out of    301    35%
604
   Number of fully used LUT-FF pairs:   126  out of    301    41%
605 20 jdoin
   Number of unique control sets:        23
606
 
607
IO Utilization:
608
 Number of IOs:                          63
609
 Number of bonded IOBs:                  63  out of    218    28%
610
 
611
Specific Feature Utilization:
612
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%
613
 
614
---------------------------
615
Partition Resource Summary:
616
---------------------------
617
 
618
  No Partitions were found in this design.
619
 
620
---------------------------
621
 
622
 
623
=========================================================================
624
Timing Report
625
 
626
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
627
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
628
      GENERATED AFTER PLACE-and-ROUTE.
629
 
630
Clock Information:
631
------------------
632
-----------------------------------+------------------------+-------+
633
Clock Signal                       | Clock buffer(FF name)  | Load  |
634
-----------------------------------+------------------------+-------+
635 22 jdoin
gclk_i                             | BUFGP                  | 203   |
636
Inst_spi_master_port/spi_clk_reg   | BUFG                   | 29    |
637 20 jdoin
-----------------------------------+------------------------+-------+
638
 
639
Asynchronous Control Signals Information:
640
----------------------------------------
641
No asynchronous control signals found in this design
642
 
643
Timing Summary:
644
---------------
645
Speed Grade: -2
646
 
647 22 jdoin
   Minimum period: 5.267ns (Maximum Frequency: 189.861MHz)
648 20 jdoin
   Minimum input arrival time before clock: 2.083ns
649 22 jdoin
   Maximum output required time after clock: 7.216ns
650 20 jdoin
   Maximum combinational path delay: No path found
651
 
652
Timing Details:
653
---------------
654
All values displayed in nanoseconds (ns)
655
 
656
=========================================================================
657
Timing constraint: Default period analysis for Clock 'gclk_i'
658 22 jdoin
  Clock period: 5.267ns (frequency: 189.861MHz)
659
  Total number of paths / destination ports: 2605 / 280
660 20 jdoin
-------------------------------------------------------------------------
661 22 jdoin
Delay:               5.267ns (Levels of Logic = 4)
662 20 jdoin
  Source:            sw_reg_5 (FF)
663 22 jdoin
  Destination:       m_wr_st_reg_FSM_FFd4 (FF)
664 20 jdoin
  Source Clock:      gclk_i rising
665
  Destination Clock: gclk_i rising
666
 
667 22 jdoin
  Data Path: sw_reg_5 to m_wr_st_reg_FSM_FFd4
668 20 jdoin
                                Gate     Net
669
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
670
    ----------------------------------------  ------------
671
     FDE:C->Q              3   0.525   1.196  sw_reg_5 (sw_reg_5)
672
     LUT6:I1->O            2   0.254   0.834  _n038082 (_n038081)
673 22 jdoin
     LUT6:I4->O            8   0.250   0.944  _n038083 (_n0380)
674
     LUT5:I4->O            1   0.254   0.682  m_wr_st_reg_FSM_FFd2-In1 (m_wr_st_reg_FSM_FFd2-In1)
675
     LUT6:I5->O            1   0.254   0.000  m_wr_st_reg_FSM_FFd2-In2 (m_wr_st_reg_FSM_FFd2-In)
676
     FDR:D                     0.074          m_wr_st_reg_FSM_FFd2
677 20 jdoin
    ----------------------------------------
678 22 jdoin
    Total                      5.267ns (1.611ns logic, 3.656ns route)
679
                                       (30.6% logic, 69.4% route)
680 20 jdoin
 
681
=========================================================================
682
Timing constraint: Default period analysis for Clock 'Inst_spi_master_port/spi_clk_reg'
683
  Clock period: 4.344ns (frequency: 230.203MHz)
684
  Total number of paths / destination ports: 214 / 36
685
-------------------------------------------------------------------------
686
Delay:               2.172ns (Levels of Logic = 2)
687
  Source:            Inst_spi_slave_port/state_reg_1_1 (FF)
688
  Destination:       Inst_spi_slave_port/tx_bit_reg (FF)
689
  Source Clock:      Inst_spi_master_port/spi_clk_reg rising
690
  Destination Clock: Inst_spi_master_port/spi_clk_reg falling
691
 
692
  Data Path: Inst_spi_slave_port/state_reg_1_1 to Inst_spi_slave_port/tx_bit_reg
693
                                Gate     Net
694
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
695
    ----------------------------------------  ------------
696
     FDC:C->Q              2   0.525   1.156  Inst_spi_slave_port/state_reg_1_1 (Inst_spi_slave_port/state_reg_1_1)
697 22 jdoin
     LUT6:I1->O            1   0.254   0.000  Inst_spi_slave_port/tx_bit_next3_F (N10)
698 20 jdoin
     MUXF7:I0->O           1   0.163   0.000  Inst_spi_slave_port/tx_bit_next3 (Inst_spi_slave_port/tx_bit_next)
699
     FD_1:D                    0.074          Inst_spi_slave_port/tx_bit_reg
700
    ----------------------------------------
701
    Total                      2.172ns (1.016ns logic, 1.156ns route)
702
                                       (46.8% logic, 53.2% route)
703
 
704
=========================================================================
705
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
706
  Total number of paths / destination ports: 14 / 14
707
-------------------------------------------------------------------------
708
Offset:              2.083ns (Levels of Logic = 1)
709
  Source:            sw_i<7> (PAD)
710
  Destination:       Inst_sw_debouncer/reg_A_7 (FF)
711
  Destination Clock: gclk_i rising
712
 
713
  Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
714
                                Gate     Net
715
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
716
    ----------------------------------------  ------------
717
     IBUF:I->O             1   1.328   0.681  sw_i_7_IBUF (sw_i_7_IBUF)
718
     FD:D                      0.074          Inst_sw_debouncer/reg_A_7
719
    ----------------------------------------
720
    Total                      2.083ns (1.402ns logic, 0.681ns route)
721
                                       (67.3% logic, 32.7% route)
722
 
723
=========================================================================
724
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
725 22 jdoin
  Total number of paths / destination ports: 37 / 31
726 20 jdoin
-------------------------------------------------------------------------
727 22 jdoin
Offset:              7.216ns (Levels of Logic = 3)
728
  Source:            Inst_spi_master_port/state_reg_2 (FF)
729
  Destination:       spi_mosi_o (PAD)
730 20 jdoin
  Source Clock:      gclk_i rising
731
 
732 22 jdoin
  Data Path: Inst_spi_master_port/state_reg_2 to spi_mosi_o
733 20 jdoin
                                Gate     Net
734
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
735
    ----------------------------------------  ------------
736 22 jdoin
     FDRE:C->Q            20   0.525   1.394  Inst_spi_master_port/state_reg_2 (Inst_spi_master_port/state_reg_2)
737
     LUT2:I0->O            2   0.250   1.156  Inst_spi_master_port/spi_mosi_o_SW0 (N0)
738
     LUT6:I1->O            2   0.254   0.725  Inst_spi_master_port/spi_mosi_o (spi_mosi_o_OBUF)
739
     OBUF:I->O                 2.912          spi_mosi_o_OBUF (spi_mosi_o)
740 20 jdoin
    ----------------------------------------
741 22 jdoin
    Total                      7.216ns (3.941ns logic, 3.275ns route)
742
                                       (54.6% logic, 45.4% route)
743 20 jdoin
 
744
=========================================================================
745
Timing constraint: Default OFFSET OUT AFTER for Clock 'Inst_spi_master_port/spi_clk_reg'
746 22 jdoin
  Total number of paths / destination ports: 19 / 18
747 20 jdoin
-------------------------------------------------------------------------
748 22 jdoin
Offset:              5.307ns (Levels of Logic = 2)
749
  Source:            Inst_spi_slave_port/preload_miso (FF)
750 20 jdoin
  Destination:       spi_miso_o (PAD)
751 22 jdoin
  Source Clock:      Inst_spi_master_port/spi_clk_reg falling
752 20 jdoin
 
753 22 jdoin
  Data Path: Inst_spi_slave_port/preload_miso to spi_miso_o
754 20 jdoin
                                Gate     Net
755
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
756
    ----------------------------------------  ------------
757 22 jdoin
     FDP_1:C->Q            2   0.525   0.954  Inst_spi_slave_port/preload_miso (Inst_spi_slave_port/preload_miso)
758
     LUT3:I0->O            1   0.235   0.681  Inst_spi_slave_port/Mmux_spi_miso_o11 (spi_miso_o_OBUF)
759 20 jdoin
     OBUF:I->O                 2.912          spi_miso_o_OBUF (spi_miso_o)
760
    ----------------------------------------
761 22 jdoin
    Total                      5.307ns (3.672ns logic, 1.635ns route)
762
                                       (69.2% logic, 30.8% route)
763 20 jdoin
 
764
=========================================================================
765
 
766
Cross Clock Domains Report:
767
--------------------------
768
 
769
Clock to Setup on destination clock Inst_spi_master_port/spi_clk_reg
770
--------------------------------+---------+---------+---------+---------+
771
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
772
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
773
--------------------------------+---------+---------+---------+---------+
774 22 jdoin
Inst_spi_master_port/spi_clk_reg|    3.682|         |    2.224|         |
775
gclk_i                          |    4.633|         |    3.198|         |
776 20 jdoin
--------------------------------+---------+---------+---------+---------+
777
 
778
Clock to Setup on destination clock gclk_i
779
--------------------------------+---------+---------+---------+---------+
780
                                | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
781
Source Clock                    |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
782
--------------------------------+---------+---------+---------+---------+
783 22 jdoin
Inst_spi_master_port/spi_clk_reg|    2.078|    1.855|         |         |
784
gclk_i                          |    5.267|         |         |         |
785 20 jdoin
--------------------------------+---------+---------+---------+---------+
786
 
787
=========================================================================
788
 
789
 
790 22 jdoin
Total REAL time to Xst completion: 6.00 secs
791
Total CPU time to Xst completion: 6.29 secs
792 20 jdoin
 
793
-->
794
 
795 22 jdoin
Total memory usage is 188108 kilobytes
796 20 jdoin
 
797
Number of errors   :    0 (   0 filtered)
798 22 jdoin
Number of warnings :   26 (   0 filtered)
799
Number of infos    :   24 (   0 filtered)
800 20 jdoin
 

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