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Release 13.1 Trace (nt)
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Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
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C:\Xilinx\13.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n
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3 -fastpaths -xml spi_master_atlys_top.twx spi_master_atlys_top.ncd -o
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spi_master_atlys_top.twr spi_master_atlys_top.pcf -ucf spi_master_atlys.ucf
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Design file: spi_master_atlys_top.ncd
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Physical constraint file: spi_master_atlys_top.pcf
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Device,package,speed: xc6slx45,csg324,C,-2 (PRODUCTION 1.18 2011-04-07)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Setup/Hold to clock pclk_i
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------------+------------+------------+------------+------------+------------------+--------+
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|Max Setup to| Process |Max Hold to | Process | | Clock |
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Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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------------+------------+------------+------------+------------+------------------+--------+
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jdoin |
btn_i<0> | 3.281(R)| SLOW | -1.883(R)| FAST |pclk_i_BUFGP | 0.000|
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btn_i<1> | 2.636(R)| SLOW | -1.373(R)| FAST |pclk_i_BUFGP | 0.000|
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btn_i<2> | 2.349(R)| SLOW | -1.227(R)| FAST |pclk_i_BUFGP | 0.000|
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btn_i<3> | 2.429(R)| SLOW | -1.296(R)| FAST |pclk_i_BUFGP | 0.000|
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btn_i<4> | 2.683(R)| SLOW | -1.357(R)| FAST |pclk_i_BUFGP | 0.000|
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btn_i<5> | 2.506(R)| SLOW | -1.310(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<0> | 4.238(R)| SLOW | -2.204(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<1> | 5.454(R)| SLOW | -2.988(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<2> | 5.564(R)| SLOW | -3.092(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<3> | 4.954(R)| SLOW | -2.667(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<4> | 3.356(R)| SLOW | -1.807(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<5> | 3.819(R)| SLOW | -2.067(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<6> | 3.504(R)| SLOW | -1.935(R)| FAST |pclk_i_BUFGP | 0.000|
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sw_i<7> | 4.898(R)| SLOW | -2.712(R)| FAST |pclk_i_BUFGP | 0.000|
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------------+------------+------------+------------+------------+------------------+--------+
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Clock pclk_i to Pad
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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jdoin |
dbg_o<4> | 10.259(R)| SLOW | 4.367(R)| FAST |pclk_i_BUFGP | 0.000|
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dbg_o<5> | 10.673(R)| SLOW | 4.584(R)| FAST |pclk_i_BUFGP | 0.000|
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dbg_o<7> | 11.287(R)| SLOW | 4.943(R)| FAST |pclk_i_BUFGP | 0.000|
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dbg_o<8> | 10.559(R)| SLOW | 4.549(R)| FAST |pclk_i_BUFGP | 0.000|
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dbg_o<9> | 11.050(R)| SLOW | 4.864(R)| FAST |pclk_i_BUFGP | 0.000|
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dbg_o<11> | 11.417(R)| SLOW | 5.029(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<0> | 10.269(R)| SLOW | 4.340(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<1> | 10.286(R)| SLOW | 4.343(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<2> | 10.086(R)| SLOW | 4.243(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<3> | 9.662(R)| SLOW | 4.013(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<4> | 10.628(R)| SLOW | 4.638(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<5> | 16.982(R)| SLOW | 8.242(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<6> | 11.879(R)| SLOW | 5.270(R)| FAST |pclk_i_BUFGP | 0.000|
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led_o<7> | 11.522(R)| SLOW | 5.043(R)| FAST |pclk_i_BUFGP | 0.000|
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spi_miso_o | 12.331(R)| SLOW | 5.494(R)| FAST |pclk_i_BUFGP | 0.000|
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spi_mosi_o | 13.082(R)| SLOW | 5.597(R)| FAST |pclk_i_BUFGP | 0.000|
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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Clock sclk_i to Pad
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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dbg_o<10> | 10.866(R)| SLOW | 4.745(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<0> | 9.804(R)| SLOW | 4.076(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<1> | 10.049(R)| SLOW | 4.245(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<2> | 9.996(R)| SLOW | 4.197(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<3> | 10.252(R)| SLOW | 4.438(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<4> | 10.157(R)| SLOW | 4.402(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<5> | 10.068(R)| SLOW | 4.306(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<6> | 10.140(R)| SLOW | 4.388(R)| FAST |sclk_i_BUFGP | 0.000|
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m_do_o<7> | 9.935(R)| SLOW | 4.259(R)| FAST |sclk_i_BUFGP | 0.000|
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m_state_o<0>| 12.092(R)| SLOW | 5.558(R)| FAST |sclk_i_BUFGP | 0.000|
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m_state_o<1>| 11.789(R)| SLOW | 5.330(R)| FAST |sclk_i_BUFGP | 0.000|
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m_state_o<2>| 12.048(R)| SLOW | 5.490(R)| FAST |sclk_i_BUFGP | 0.000|
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m_state_o<3>| 12.089(R)| SLOW | 5.504(R)| FAST |sclk_i_BUFGP | 0.000|
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spi_mosi_o | 13.069(R)| SLOW | 5.577(R)| FAST |sclk_i_BUFGP | 0.000|
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spi_sck_o | 11.491(R)| SLOW | 5.149(R)| FAST |sclk_i_BUFGP | 0.000|
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spi_ssel_o | 12.854(R)| SLOW | 5.864(R)| FAST |sclk_i_BUFGP | 0.000|
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------------+-----------------+------------+-----------------+------------+------------------+--------+
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Clock to Setup on destination clock pclk_i
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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pclk_i | 5.916| | | |
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sclk_i | 4.466| | | |
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---------------+---------+---------+---------+---------+
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Clock to Setup on destination clock sclk_i
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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pclk_i | 3.370| | | |
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sclk_i | 3.391| | | |
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---------------+---------+---------+---------+---------+
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Analysis completed Thu Sep 01 13:07:46 2011
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 180 MB
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