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jdoin |
Release 13.1 Map O.40d (nt)
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Xilinx Map Application Log File for Design 'spi_master_atlys_top'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
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high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
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-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
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off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd
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spi_master_atlys_top.pcf
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Target Device : xc6slx45
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Target Package : csg324
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Target Speed : -2
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Mapper Version : spartan6 -- $Revision: 1.55 $
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Mapped Date : Wed Aug 10 22:56:29 2011
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Running global optimization...
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Updating timing models...
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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Running timing-driven placement...
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Total REAL time at the beginning of Placer: 10 secs
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Total CPU time at the beginning of Placer: 9 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:542d7d4b) REAL time: 11 secs
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Phase 2.7 Design Feasibility Check
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INFO:Place:834 - Only a subset of IOs are locked. Out of 63 IOs, 43 are locked
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and 20 are not locked. If you would like to print the names of these IOs,
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please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
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Phase 2.7 Design Feasibility Check (Checksum:542d7d4b) REAL time: 11 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:542d7d4b) REAL time: 11 secs
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Phase 4.2 Initial Placement for Architecture Specific Features
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...
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Phase 4.2 Initial Placement for Architecture Specific Features
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(Checksum:23369eb) REAL time: 16 secs
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Phase 5.36 Local Placement Optimization
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Phase 5.36 Local Placement Optimization (Checksum:23369eb) REAL time: 16 secs
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Phase 6.30 Global Clock Region Assignment
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Phase 6.30 Global Clock Region Assignment (Checksum:23369eb) REAL time: 16 secs
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Phase 7.3 Local Placement Optimization
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...
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Phase 7.3 Local Placement Optimization (Checksum:c4747df0) REAL time: 16 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:c4747df0) REAL time: 16 secs
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Phase 9.8 Global Placement
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...........
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.....
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Phase 9.8 Global Placement (Checksum:55e2a6f9) REAL time: 17 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:55e2a6f9) REAL time: 17 secs
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Phase 11.18 Placement Optimization
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Phase 11.18 Placement Optimization (Checksum:402bf1c7) REAL time: 18 secs
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Phase 12.5 Local Placement Optimization
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Phase 12.5 Local Placement Optimization (Checksum:402bf1c7) REAL time: 18 secs
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Phase 13.34 Placement Validation
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Phase 13.34 Placement Validation (Checksum:55d3da5) REAL time: 18 secs
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Total REAL time to Placer completion: 18 secs
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Total CPU time to Placer completion: 16 secs
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Running post-placement packing...
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Writing output files...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 0
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Slice Logic Utilization:
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Number of Slice Registers: 209 out of 54,576 1%
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Number used as Flip Flops: 209
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Number used as Latches: 0
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Number used as Latch-thrus: 0
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Number used as AND/OR logics: 0
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Number of Slice LUTs: 145 out of 27,288 1%
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Number used as logic: 127 out of 27,288 1%
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Number using O6 output only: 75
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Number using O5 output only: 13
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Number using O5 and O6: 39
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Number used as ROM: 0
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Number used as Memory: 4 out of 6,408 1%
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Number used as Dual Port RAM: 0
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Number used as Single Port RAM: 0
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Number used as Shift Register: 4
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Number using O6 output only: 4
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Number using O5 output only: 0
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Number using O5 and O6: 0
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Number used exclusively as route-thrus: 14
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Number with same-slice register load: 12
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Number with same-slice carry load: 2
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Number with other load: 0
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Slice Logic Distribution:
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Number of occupied Slices: 91 out of 6,822 1%
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Number of LUT Flip Flop pairs used: 225
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Number with an unused Flip Flop: 49 out of 225 21%
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Number with an unused LUT: 80 out of 225 35%
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Number of fully used LUT-FF pairs: 96 out of 225 42%
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Number of unique control sets: 25
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Number of slice register sites lost
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to control set restrictions: 59 out of 54,576 1%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 63 out of 218 28%
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Number of LOCed IOBs: 43 out of 63 68%
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 116 0%
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Number of RAMB8BWERs: 0 out of 232 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 2 out of 16 12%
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Number used as BUFGs: 2
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Number used as BUFGMUX: 0
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Number of DCM/DCM_CLKGENs: 0 out of 8 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
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Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 256 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 58 0%
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Number of ICAPs: 0 out of 1 0%
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Number of MCBs: 0 out of 2 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 4 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 2.81
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Peak Memory Usage: 303 MB
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Total REAL time to MAP completion: 19 secs
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Total CPU time to MAP completion (all processors): 17 secs
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Mapping completed.
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See MAP report file "spi_master_atlys_top_map.mrp" for details.
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