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[/] [spi_master_slave/] [trunk/] [syn/] [spi_master_atlys_top_map.mrp] - Blame information for rev 24

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1 20 jdoin
Release 13.1 Map O.40d (nt)
2
Xilinx Mapping Report File for Design 'spi_master_atlys_top'
3
 
4
Design Information
5
------------------
6
Command Line   : map -intstyle ise -p xc6slx45-csg324-2 -w -logic_opt off -ol
7
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt area
8
-equivalent_register_removal on -mt 2 -detail -ir off -pr off -lc area -power
9
off -o spi_master_atlys_top_map.ncd spi_master_atlys_top.ngd
10
spi_master_atlys_top.pcf
11
Target Device  : xc6slx45
12
Target Package : csg324
13
Target Speed   : -2
14
Mapper Version : spartan6 -- $Revision: 1.55 $
15 24 jdoin
Mapped Date    : Thu Sep 01 13:07:11 2011
16 20 jdoin
 
17
Design Summary
18
--------------
19
Number of errors:      0
20
Number of warnings:    0
21
Slice Logic Utilization:
22 24 jdoin
  Number of Slice Registers:                   210 out of  54,576    1%
23
    Number used as Flip Flops:                 210
24 20 jdoin
    Number used as Latches:                      0
25
    Number used as Latch-thrus:                  0
26
    Number used as AND/OR logics:                0
27 24 jdoin
  Number of Slice LUTs:                        143 out of  27,288    1%
28
    Number used as logic:                      129 out of  27,288    1%
29
      Number using O6 output only:              79
30
      Number using O5 output only:              15
31
      Number using O5 and O6:                   35
32 20 jdoin
      Number used as ROM:                        0
33
    Number used as Memory:                       4 out of   6,408    1%
34
      Number used as Dual Port RAM:              0
35
      Number used as Single Port RAM:            0
36
      Number used as Shift Register:             4
37
        Number using O6 output only:             4
38
        Number using O5 output only:             0
39
        Number using O5 and O6:                  0
40 24 jdoin
    Number used exclusively as route-thrus:     10
41
      Number with same-slice register load:      8
42 20 jdoin
      Number with same-slice carry load:         2
43
      Number with other load:                    0
44
 
45
Slice Logic Distribution:
46 24 jdoin
  Number of occupied Slices:                    91 out of   6,822    1%
47
  Number of LUT Flip Flop pairs used:          231
48
    Number with an unused Flip Flop:            46 out of     231   19%
49
    Number with an unused LUT:                  88 out of     231   38%
50
    Number of fully used LUT-FF pairs:          97 out of     231   41%
51
    Number of unique control sets:              27
52 20 jdoin
    Number of slice register sites lost
53 24 jdoin
      to control set restrictions:              74 out of  54,576    1%
54 20 jdoin
 
55
  A LUT Flip Flop pair for this architecture represents one LUT paired with
56
  one Flip Flop within a slice.  A control set is a unique combination of
57
  clock, reset, set, and enable signals for a registered element.
58
  The Slice Logic Distribution report is not meaningful if the design is
59
  over-mapped for a non-slice resource or if Placement fails.
60
 
61
IO Utilization:
62 24 jdoin
  Number of bonded IOBs:                        64 out of     218   29%
63
    Number of LOCed IOBs:                       46 out of      64   71%
64 20 jdoin
 
65
Specific Feature Utilization:
66
  Number of RAMB16BWERs:                         0 out of     116    0%
67
  Number of RAMB8BWERs:                          0 out of     232    0%
68
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
69
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
70 24 jdoin
  Number of BUFG/BUFGMUXs:                       3 out of      16   18%
71
    Number used as BUFGs:                        3
72 20 jdoin
    Number used as BUFGMUX:                      0
73
  Number of DCM/DCM_CLKGENs:                     0 out of       8    0%
74
  Number of ILOGIC2/ISERDES2s:                   0 out of     376    0%
75
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     376    0%
76
  Number of OLOGIC2/OSERDES2s:                   0 out of     376    0%
77
  Number of BSCANs:                              0 out of       4    0%
78
  Number of BUFHs:                               0 out of     256    0%
79
  Number of BUFPLLs:                             0 out of       8    0%
80
  Number of BUFPLL_MCBs:                         0 out of       4    0%
81
  Number of DSP48A1s:                            0 out of      58    0%
82
  Number of ICAPs:                               0 out of       1    0%
83
  Number of MCBs:                                0 out of       2    0%
84
  Number of PCILOGICSEs:                         0 out of       2    0%
85
  Number of PLL_ADVs:                            0 out of       4    0%
86
  Number of PMVs:                                0 out of       1    0%
87
  Number of STARTUPs:                            0 out of       1    0%
88
  Number of SUSPEND_SYNCs:                       0 out of       1    0%
89
 
90 24 jdoin
Average Fanout of Non-Clock Nets:                2.86
91 20 jdoin
 
92 24 jdoin
Peak Memory Usage:  301 MB
93 22 jdoin
Total REAL time to MAP completion:  17 secs
94 20 jdoin
Total CPU time to MAP completion (all processors):   17 secs
95
 
96
Table of Contents
97
-----------------
98
Section 1 - Errors
99
Section 2 - Warnings
100
Section 3 - Informational
101
Section 4 - Removed Logic Summary
102
Section 5 - Removed Logic
103
Section 6 - IOB Properties
104
Section 7 - RPMs
105
Section 8 - Guide Report
106
Section 9 - Area Group and Partition Summary
107
Section 10 - Timing Report
108
Section 11 - Configuration String Information
109
Section 12 - Control Set Information
110
Section 13 - Utilization by Hierarchy
111
 
112
Section 1 - Errors
113
------------------
114
 
115
Section 2 - Warnings
116
--------------------
117
 
118
Section 3 - Informational
119
-------------------------
120
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
121
   supports the use of up to 2 processors. Based on the the user options and
122
   machine load, Map will use 2 processors during this run.
123
INFO:Xst:2261 - The FF/Latch  in Unit
124
    is equivalent to the following FF/Latch, which will be
125
   removed : 
126
INFO:Xst:2261 - The FF/Latch  in Unit
127
    is equivalent to the following FF/Latch, which will be
128
   removed : 
129
INFO:Xst:2261 - The FF/Latch  in Unit
130
    is equivalent to the following 2 FFs/Latches, which
131
   will be removed : 
132
   
133 24 jdoin
INFO:LIT:243 - Logical network pclk_i_BUFGP/N2 has no load.
134
INFO:LIT:243 - Logical network pclk_i_BUFGP/N3 has no load.
135
INFO:LIT:243 - Logical network sclk_i_BUFGP/N2 has no load.
136
INFO:LIT:243 - Logical network sclk_i_BUFGP/N3 has no load.
137 20 jdoin
INFO:MapLib:562 - No environment variables are currently set.
138
INFO:LIT:244 - All of the single ended outputs in this design are using slew
139
   rate limited output drivers. The delay on speed critical single ended outputs
140
   can be dramatically reduced by designating them as fast outputs.
141
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
142
   0.000 to 85.000 Celsius)
143
INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
144
   1.260 Volts)
145
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
146
   (.mrp).
147 24 jdoin
INFO:Place:834 - Only a subset of IOs are locked. Out of 64 IOs, 46 are locked
148
   and 18 are not locked. If you would like to print the names of these IOs,
149 20 jdoin
   please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.
150
INFO:Pack:1650 - Map created a placed design.
151
 
152
Section 4 - Removed Logic Summary
153
---------------------------------
154 24 jdoin
   4 block(s) removed
155 20 jdoin
   2 block(s) optimized away
156 24 jdoin
   4 signal(s) removed
157
  58 Block(s) redundant
158 20 jdoin
 
159
Section 5 - Removed Logic
160
-------------------------
161
 
162
The trimmed logic report below shows the logic removed from your design due to
163
sourceless or loadless signals, and VCC or ground connections.  If the removal
164
of a signal or symbol results in the subsequent removal of an additional signal
165
or symbol, the message explaining that second removal will be indented.  This
166
indentation will be repeated as a chain of related logic is removed.
167
 
168
To quickly locate the original cause for the removal of a chain of logic, look
169
above the place where that logic is listed in the trimming report, then locate
170
the lines that are least indented (begin at the leftmost edge).
171
 
172 24 jdoin
The signal "pclk_i_BUFGP/N2" is sourceless and has been removed.
173
The signal "pclk_i_BUFGP/N3" is sourceless and has been removed.
174
The signal "sclk_i_BUFGP/N2" is sourceless and has been removed.
175
The signal "sclk_i_BUFGP/N3" is sourceless and has been removed.
176
Unused block "pclk_i_BUFGP/XST_GND" (ZERO) removed.
177
Unused block "pclk_i_BUFGP/XST_VCC" (ONE) removed.
178
Unused block "sclk_i_BUFGP/XST_GND" (ZERO) removed.
179
Unused block "sclk_i_BUFGP/XST_VCC" (ONE) removed.
180 20 jdoin
 
181
Optimized Block(s):
182
TYPE            BLOCK
183
GND             XST_GND
184
VCC             XST_VCC
185
 
186
Redundant Block(s):
187
TYPE            BLOCK
188
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<6>_rt
189
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<5>_rt
190
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<4>_rt
191
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<3>_rt
192
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<2>_rt
193
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_cy<1>_rt
194
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<6>_rt
195
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<5>_rt
196
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<4>_rt
197
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<3>_rt
198
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<2>_rt
199
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_cy<1>_rt
200 24 jdoin
LUT1            Inst_sw_debouncer/Mcount_cnt_reg_xor<7>_rt
201
LUT1            Inst_btn_debouncer/Mcount_cnt_reg_xor<7>_rt
202
INV             ][241_70_INV_0
203
INV             ][245_78_INV_0
204
INV             ][249_83_INV_0
205
INV             ][253_88_INV_0
206
INV             ][257_93_INV_0
207
INV             ][261_98_INV_0
208
INV             ][269_106_INV_0
209
INV             ][369_161_INV_0
210
INV             ][373_166_INV_0
211
INV             ][389_179_INV_0
212
INV             ][397_186_INV_0
213
INV             ][401_190_INV_0
214
INV             ][402_194_INV_0
215
INV             ][405_196_INV_0
216
INV             ][409_201_INV_0
217
INV             ][413_206_INV_0
218
INV             ][417_211_INV_0
219
INV             ][421_216_INV_0
220
INV             ][425_221_INV_0
221
INV             ][429_226_INV_0
222
INV             ][453_249_INV_0
223
INV             ][461_256_INV_0
224
INV             ][465_260_INV_0
225
INV             ][469_264_INV_0
226
INV             ][645_373_INV_0
227
INV             ][649_378_INV_0
228
INV             ][653_382_INV_0
229
INV             ][657_386_INV_0
230
INV             ][661_390_INV_0
231
INV             ][665_394_INV_0
232
INV             ][669_398_INV_0
233
INV             ][673_402_INV_0
234
INV             ][694_417_INV_0
235
INV             ][725_439_INV_0
236
INV             ][729_444_INV_0
237
INV             ][803_502_INV_0
238
INV             ][836_526_INV_0
239
INV             ][841_529_INV_0
240
INV             ][878_552_INV_0
241
INV             ][881_556_INV_0
242
INV             ][918_585_INV_0
243
INV             ][921_589_INV_0
244
INV             ][927_596_INV_0
245
INV             ][930_600_INV_0
246 20 jdoin
 
247
Section 6 - IOB Properties
248
--------------------------
249
 
250
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
251
| IOB Name                           | Type             | Direction | IO Standard          | Diff  | Drive    | Slew | Reg (s)      | Resistor | IOB      |
252
|                                    |                  |           |                      | Term  | Strength | Rate |              |          | Delay    |
253
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
254
| btn_i<0>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
255
| btn_i<1>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
256
| btn_i<2>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
257
| btn_i<3>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
258
| btn_i<4>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
259
| btn_i<5>                           | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
260
| dbg_o<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
261
| dbg_o<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
262
| dbg_o<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
263
| dbg_o<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
264
| dbg_o<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
265
| dbg_o<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
266
| dbg_o<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
267
| dbg_o<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
268
| dbg_o<8>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
269
| dbg_o<9>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
270
| dbg_o<10>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
271
| dbg_o<11>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
272
| led_o<0>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
273
| led_o<1>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
274
| led_o<2>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
275
| led_o<3>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
276
| led_o<4>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
277
| led_o<5>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
278
| led_o<6>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
279
| led_o<7>                           | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
280
| m_do_o<0>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
281
| m_do_o<1>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
282
| m_do_o<2>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
283
| m_do_o<3>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
284
| m_do_o<4>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
285
| m_do_o<5>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
286
| m_do_o<6>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
287
| m_do_o<7>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
288
| m_state_o<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
289
| m_state_o<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
290
| m_state_o<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
291
| m_state_o<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
292 24 jdoin
| pclk_i                             | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
293 20 jdoin
| s_do_o<0>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
294
| s_do_o<1>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
295
| s_do_o<2>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
296
| s_do_o<3>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
297
| s_do_o<4>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
298
| s_do_o<5>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
299
| s_do_o<6>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
300
| s_do_o<7>                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
301
| s_state_o<0>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
302
| s_state_o<1>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
303
| s_state_o<2>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
304
| s_state_o<3>                       | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
305 24 jdoin
| sclk_i                             | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
306 20 jdoin
| spi_miso_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
307
| spi_mosi_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
308
| spi_sck_o                          | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
309
| spi_ssel_o                         | IOB              | OUTPUT    | LVCMOS25             |       | 12       | SLOW |              |          |          |
310
| sw_i<0>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
311
| sw_i<1>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
312
| sw_i<2>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
313
| sw_i<3>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
314
| sw_i<4>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
315
| sw_i<5>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
316
| sw_i<6>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
317
| sw_i<7>                            | IOB              | INPUT     | LVCMOS25             |       |          |      |              |          |          |
318
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
319
 
320
Section 7 - RPMs
321
----------------
322
 
323
Section 8 - Guide Report
324
------------------------
325
Guide not run on this design.
326
 
327
Section 9 - Area Group and Partition Summary
328
--------------------------------------------
329
 
330
Partition Implementation Status
331
-------------------------------
332
 
333
  No Partitions were found in this design.
334
 
335
-------------------------------
336
 
337
Area Group Information
338
----------------------
339
 
340
  No area groups were found in this design.
341
 
342
----------------------
343
 
344
Section 10 - Timing Report
345
--------------------------
346
A logic-level (pre-route) timing report can be generated by using Xilinx static
347
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
348
mapped NCD and PCF files. Please note that this timing report will be generated
349
using estimated delay information. For accurate numbers, please generate a
350
timing report with the post Place and Route NCD file.
351
 
352
For more information about the Timing Analyzer, consult the Xilinx Timing
353
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
354
Command Line Tools User Guide "TRACE" chapter.
355
 
356
Section 11 - Configuration String Details
357
-----------------------------------------
358
 
359
Section 12 - Control Set Information
360
------------------------------------
361
+-----------------------------------------------------------------------------------------------------------------------------------+
362
| Clock Signal                           | Reset Signal           | Set Signal | Enable Signal  | Slice Load Count | Bel Load Count |
363
+-----------------------------------------------------------------------------------------------------------------------------------+
364
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            |                | 6                | 11             |
365 24 jdoin
| Inst_spi_master_port/spi_clk_reg_BUFG  |                        |            | lut1157_481    | 2                | 8              |
366
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][1041_0               |            |                | 2                | 2              |
367
| Inst_spi_master_port/spi_clk_reg_BUFG  | ][IN_virtPIBox_541_658 |            |                | 1                | 2              |
368 20 jdoin
+-----------------------------------------------------------------------------------------------------------------------------------+
369 24 jdoin
| pclk_i_BUFGP                           |                        |            |                | 28               | 67             |
370
| pclk_i_BUFGP                           |                        |            | GLOBAL_LOGIC1  | 1                | 4              |
371
| pclk_i_BUFGP                           |                        |            | ][210_33       | 1                | 8              |
372
| pclk_i_BUFGP                           |                        |            | ][242_76       | 2                | 6              |
373
| pclk_i_BUFGP                           |                        |            | ][402_194      | 2                | 8              |
374
| pclk_i_BUFGP                           |                        |            | lut410_104     | 1                | 2              |
375
| pclk_i_BUFGP                           |                        |            | lut422_111     | 2                | 8              |
376
| pclk_i_BUFGP                           |                        |            | lut463_128     | 2                | 8              |
377
| pclk_i_BUFGP                           |                        |            | lut504_145     | 2                | 8              |
378
| pclk_i_BUFGP                           |                        |            | lut546_164     | 2                | 8              |
379
| pclk_i_BUFGP                           |                        |            | lut710_270     | 2                | 8              |
380
| pclk_i_BUFGP                           |                        |            | lut832_320     | 2                | 6              |
381
| pclk_i_BUFGP                           |                        |            | spi_wren_reg_m | 1                | 8              |
382
| pclk_i_BUFGP                           |                        |            | spi_wren_reg_s | 1                | 2              |
383
| pclk_i_BUFGP                           | ][1041_0               |            |                | 2                | 6              |
384
| pclk_i_BUFGP                           | clear                  |            |                | 2                | 4              |
385 20 jdoin
+-----------------------------------------------------------------------------------------------------------------------------------+
386 24 jdoin
| sclk_i_BUFGP                           |                        |            |                | 3                | 4              |
387
| sclk_i_BUFGP                           |                        |            | ][691_415      | 3                | 4              |
388
| sclk_i_BUFGP                           |                        |            | lut923_357     | 2                | 8              |
389
| sclk_i_BUFGP                           |                        |            | lut965_376     | 2                | 8              |
390
| sclk_i_BUFGP                           | spi_rst_reg            |            | ][691_415      | 1                | 4              |
391
+-----------------------------------------------------------------------------------------------------------------------------------+
392 20 jdoin
| ~Inst_spi_master_port/spi_clk_reg_BUFG |                        |            |                | 1                | 1              |
393 24 jdoin
| ~Inst_spi_master_port/spi_clk_reg_BUFG | ][1041_0               |            |                | 1                | 1              |
394 20 jdoin
+-----------------------------------------------------------------------------------------------------------------------------------+
395
 
396
Section 13 - Utilization by Hierarchy
397
-------------------------------------
398
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
399
| Module                | Partition | Slices*       | Slice Reg     | LUTs          | LUTRAM        | BRAM/FIFO | DSP48A1 | BUFG  | BUFIO | BUFR  | DCM   | PLL_ADV   | Full Hierarchical Name                     |
400
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
401 24 jdoin
| spi_master_atlys_top/ |           | 65/122        | 71/210        | 111/121       | 0/4           | 0/0       | 0/0     | 2/3   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top                       |
402
| +Inst_btn_debouncer   |           | 9/9           | 26/26         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_btn_debouncer    |
403
| +Inst_spi_master_port |           | 18/18         | 45/45         | 2/2           | 2/2           | 0/0       | 0/0     | 1/1   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_master_port  |
404
| +Inst_spi_slave_port  |           | 20/20         | 36/36         | 6/6           | 2/2           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_spi_slave_port   |
405
| +Inst_sw_debouncer    |           | 10/10         | 32/32         | 1/1           | 0/0           | 0/0       | 0/0     | 0/0   | 0/0   | 0/0   | 0/0   | 0/0       | spi_master_atlys_top/Inst_sw_debouncer     |
406 20 jdoin
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
407
 
408
* Slices can be packed with basic elements from multiple hierarchies.
409
  Therefore, a slice will be counted in every hierarchical module
410
  that each of its packed basic elements belong to.
411
** For each column, there are two numbers reported /.
412
    is the number of elements that belong to that specific hierarchical module.
413
    is the total number of elements from that hierarchical module and any lower level
414
   hierarchical modules below.
415
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.

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