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1 10 jdoin
----------------------------------------------------------------------------------
2
-- Author:          Jonny Doin, jdoin@opencores.org
3
-- 
4
-- Create Date:     15:36:20 05/15/2011
5
-- Module Name:     SPI_SLAVE - RTL
6
-- Project Name:    SPI INTERFACE
7
-- Target Devices:  Spartan-6
8
-- Tool versions:   ISE 13.1
9
-- Description: 
10
--
11
--      This block is the SPI slave interface, implemented in one single entity.
12
--      All internal core operations are synchronous to the external SPI clock, and follows the general SPI de-facto standard.
13
--      The parallel read/write interface is synchronous to a supplied system master clock, 'clk_i'.
14
--      Synchronization for the parallel ports is provided by input data request and write enable lines, and output data valid line.
15
--      Fully pipelined cross-clock circuitry guarantees that no setup artifacts occur on the buffers that are accessed by the two 
16
--      clock domains.
17
--
18
--      The block is very simple to use, and has parallel inputs and outputs that behave like a synchronous memory i/o.
19
--      It is parameterizable via generics for the data width ('N'), SPI mode (CPHA and CPOL), and lookahead prefetch 
20
--      signaling ('PREFETCH').
21
--
22
--      PARALLEL WRITE INTERFACE
23
--      The parallel interface has a input port 'di_i' and an output port 'do_o'.
24
--      Parallel load is controlled using 3 signals: 'di_i', 'di_req_o' and 'wren_i'. 
25
--      When the core needs input data, a look ahead data request strobe , 'di_req_o' is pulsed 'PREFETCH' 'spi_sck_i' 
26
--      cycles in advance to synchronize a user pipelined memory or fifo to present the next input data at 'di_i' 
27
--      in time to have continuous clock at the spi bus, to allow back-to-back continuous load.
28
--      The data request strobe on 'di_req_o' is 2 'clk_i' clock cycles long.
29
--      The write to 'di_i' must occur at most one 'spi_sck_i' cycle before actual load to the core shift register, to avoid
30
--      race conditions at the register transfer.
31
--      The user circuit places data at the 'di_i' port and strobes the 'wren_i' line for one rising edge of 'clk_i'.
32
--      For a pipelined sync RAM, a PREFETCH of 3 cycles allows an address generator to present the new adress to the RAM in one
33
--      cycle, and the RAM to respond in one more cycle, in time for 'di_i' to be latched by the interface one clock before transfer.
34
--      If the user sequencer needs a different value for PREFETCH, the generic can be altered at instantiation time.
35
--      The 'wren_i' write enable strobe must be valid at least one setup time before the rising edge of the last clock cycle,
36
--      if continuous transmission is intended. 
37
--      When the interface is idle ('spi_ssel_i' is HIGH), the top bit of the latched 'di_i' port is presented at port 'spi_miso_o'.
38
--
39
--      PARALLEL WRITE PIPELINED SEQUENCE
40
--      =================================
41
--                     __    __    __    __    __    __    __ 
42
--      clk_i       __/  \__/  \__/  \__/  \__/  \__/  \__/  \...     -- parallel interface clock
43
--                           ___________                        
44
--      di_req_o    ________/           \_____________________...     -- 'di_req_o' asserted on rising edge of 'clk_i'
45
--                  ______________ ___________________________...
46
--      di_i        __old_data____X______new_data_____________...     -- user circuit loads data on 'di_i' at next 'clk_i' rising edge
47
--                                             ________                        
48
--      wren_i      __________________________/        \______...     -- 'wren_i' enables latch on rising edge of 'clk_i'
49
--                      
50
--
51
--      PARALLEL READ INTERFACE
52
--      An internal buffer is used to copy the internal shift register data to drive the 'do_o' port. When a complete 
53
--      word is received, the core shift register is transferred to the buffer, at the rising edge of the spi clock, 'spi_sck_i'.
54
--      The signal 'do_valid_o' is strobed 3 'clk_i' clocks after, to directly drive a synchronous memory or fifo write enable.
55
--      'do_valid_o' is synchronous to the parallel interface clock, and changes only on rising edges of 'clk_i'.
56
--      When the interface is idle, data at the 'do_o' port holds the last word received.
57
--
58
--      PARALLEL READ PIPELINED SEQUENCE
59
--      ================================
60
--                      ______        ______        ______        ______
61
--      clk_spi_i   ___/ bit1 \______/ bitN \______/bitN-1\______/bitN-2\__...  -- spi base clock
62
--                     __    __    __    __    __    __    __    __    __  
63
--      clk_i       __/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \__/  \_...  -- parallel interface clock
64
--                  _________________ _____________________________________...  -- 1) received data is transferred to 'do_buffer_reg'
65
--      do_o        __old_data_______X__________new_data___________________...  --    after last bit received, at next shift clock.
66
--                                                   ____________               
67
--      do_valid_o  ________________________________/            \_________...  -- 2) 'do_valid_o' strobed for 2 'clk_i' cycles
68
--                                                                              --    on the 3rd 'clk_i' rising edge.
69
--
70
--
71
--      This design was originally targeted to a Spartan-6 platform, synthesized with XST and normal constraints.
72
--
73
------------------------------ COPYRIGHT NOTICE -----------------------------------------------------------------------
74
--                                                                   
75
--      This file is part of the SPI MASTER/SLAVE INTERFACE project http://opencores.org/project,spi_master_slave                
76
--                                                                   
77
--      Author(s):      Jonny Doin, jdoin@opencores.org
78
--                                                                   
79
--      Copyright (C) 2011 Authors and OPENCORES.ORG
80
--      --------------------------------------------
81
--                                                                   
82
--      This source file may be used and distributed without restriction provided that this copyright statement is not    
83
--      removed from the file and that any derivative work contains the original copyright notice and the associated 
84
--      disclaimer. 
85
--                                                                   
86
--      This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser 
87
--      General Public License as published by the Free Software Foundation; either version 2.1 of the License, or 
88
--      (at your option) any later version.
89
--                                                                   
90
--      This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
91
--      warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more  
92
--      details.
93
--
94
--      You should have received a copy of the GNU Lesser General Public License along with this source; if not, download 
95
--      it from http://www.opencores.org/lgpl.shtml
96
--                                                                   
97
------------------------------ REVISION HISTORY -----------------------------------------------------------------------
98
--
99
-- 2011/05/15   v0.10.0050  [JD]    created the slave logic, with 2 clock domains, from SPI_MASTER module.
100
-- 2011/05/15   v0.15.0055  [JD]    fixed logic for starting state when CPHA='1'.
101
-- 2011/05/17   v0.80.0049  [JD]    added explicit clock synchronization circuitry across clock boundaries.
102
-- 2011/05/18   v0.95.0050  [JD]    clock generation circuitry, with generators for all-rising-edge clock core.
103
-- 2011/06/05   v0.96.0053  [JD]    changed async clear to sync resets.
104
-- 2011/06/07   v0.97.0065  [JD]    added cross-clock buffers, fixed fsm async glitches.
105
-- 2011/06/09   v0.97.0068  [JD]    reduced control sets (resets, CE, presets) to the absolute minimum to operate, to reduce 
106
--                                  synthesis LUT overhead in Spartan-6 architecture.
107
-- 2011/06/11   v0.97.0075  [JD]    redesigned all parallel data interfacing ports, and implemented cross-clock strobe logic.
108 12 jdoin
-- 2011/06/12   v0.97.0079  [JD]    implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
109
-- 2011/06/17   v0.97.0079  [JD]    implemented wr_ack and di_req logic for state 0, and eliminated unnecessary registers reset.
110 10 jdoin
-- 2011/07/16   v1.11.0080  [JD]    verified both spi_master and spi_slave in loopback at 50MHz SPI clock.
111 12 jdoin
-- 2011/07/29   v2.00.0110  [JD]    FIX: CPHA bugs:
112
--                                      - redesigned core clocking to address all CPOL and CPHA configurations.
113
--                                      - added CHANGE_EDGE to the FSM register transfer logic, to have MISO change at opposite 
114
--                                        clock phases from SHIFT_EDGE.
115
--                                  Removed global signal setting at the FSM, implementing exhaustive explicit signal attributions
116
--                                  for each state, to avoid reported inference problems in some synthesis engines.
117
--                                  Streamlined port names and indentation blocks.
118 13 jdoin
-- 2011/08/01   v2.01.0115  [JD]    Adjusted 'do_valid_o' pulse width to be 2 'clk_i', as in the master core.
119
--                                  Simulated in iSim with the master core for continuous transmission mode.
120
-- 2011/08/02   v2.02.0120  [JD]    Added mux for MISO at reset state, to output di(N-1) at start. This fixed a bug in first bit.
121
--                                  The master and slave cores were verified in FPGA with continuous transmission, for all SPI modes.
122 16 jdoin
-- 2011/08/04   v2.02.0121  [JD]    Changed minor comment bugs in the combinatorial fsm logic.
123 18 jdoin
-- 2011/08/08   v2.02.0122  [JD]    FIX: continuous transfer mode bug. When wren_i is not strobed prior to state 1 (last bit), the
124
--                                  sequencer goes to state 0, and then to state 'N' again. This produces a wrong bit-shift for received
125
--                                  data. The fix consists in engaging continuous transfer regardless of the user strobing write enable, and
126
--                                  sequencing from state 1 to N as long as the master clock is present. If the user does not write new 
127
--                                  data, the last data word is repeated.
128 10 jdoin
--
129
--                                                                   
130
-----------------------------------------------------------------------------------------------------------------------
131
--  TODO
132
--  ====
133
--
134
-----------------------------------------------------------------------------------------------------------------------
135 13 jdoin
library ieee;
136
use ieee.std_logic_1164.all;
137
use ieee.numeric_std.all;
138
use ieee.std_logic_unsigned.all;
139 10 jdoin
 
140
entity spi_slave is
141
    Generic (
142
        N : positive := 32;                                             -- 32bit serial word length is default
143
        CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
144
        CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
145
        PREFETCH : positive := 3);                                      -- prefetch lookahead cycles
146
    Port (
147
        clk_i : in std_logic := 'X';                                    -- internal interface clock (clocks di/do registers)
148
        spi_ssel_i : in std_logic := 'X';                               -- spi bus slave select line
149
        spi_sck_i : in std_logic := 'X';                                -- spi bus sck clock (clocks the shift register core)
150
        spi_mosi_i : in std_logic := 'X';                               -- spi bus mosi input
151
        spi_miso_o : out std_logic := 'X';                              -- spi bus spi_miso_o output
152
        di_req_o : out std_logic;                                       -- preload lookahead data request line
153
        di_i : in  std_logic_vector (N-1 downto 0) := (others => 'X');  -- parallel load data in (clocked in on rising edge of clk_i)
154
        wren_i : in std_logic := 'X';                                   -- user data write enable
155 12 jdoin
        wr_ack_o : out std_logic;                                       -- write acknowledge
156 10 jdoin
        do_valid_o : out std_logic;                                     -- do_o data valid strobe, valid during one clk_i rising edge.
157
        do_o : out  std_logic_vector (N-1 downto 0);                    -- parallel output (clocked out on falling clk_i)
158
        --- debug ports: can be removed for the application circuit ---
159
        do_transfer_o : out std_logic;                                  -- debug: internal transfer driver
160
        wren_o : out std_logic;                                         -- debug: internal state of the wren_i pulse stretcher
161 12 jdoin
        rx_bit_next_o : out std_logic;                                  -- debug: internal rx bit
162 13 jdoin
        state_dbg_o : out std_logic_vector (3 downto 0);                -- debug: internal state register
163 10 jdoin
        sh_reg_dbg_o : out std_logic_vector (N-1 downto 0)              -- debug: internal shift register
164
    );
165
end spi_slave;
166
 
167
--================================================================================================================
168
-- SYNTHESIS CONSIDERATIONS
169
-- ========================
170
-- There are several output ports that are used to simulate and verify the core operation. 
171
-- Do not map any signals to the unused ports, and the synthesis tool will remove the related interfacing
172
-- circuitry. 
173
-- The same is valid for the transmit and receive ports. If the receive ports are not mapped, the
174
-- synthesis tool will remove the receive logic from the generated circuitry.
175
--================================================================================================================
176
 
177 13 jdoin
architecture rtl of spi_slave is
178 10 jdoin
    -- constants to control FlipFlop synthesis
179 12 jdoin
    constant SHIFT_EDGE  : std_logic := (CPOL xnor CPHA);   -- MOSI data is captured and shifted at this SCK edge
180
    constant CHANGE_EDGE : std_logic := (CPOL xor CPHA);    -- MISO data is updated at this SCK edge
181
 
182
    ------------------------------------------------------------------------------------------
183 10 jdoin
    -- GLOBAL RESET:
184
    --      all signals are initialized to zero at GSR (global set/reset) by giving explicit
185
    --      initialization values at declaration. This is needed for all Xilinx FPGAs, and 
186
    --      especially for the Spartan-6 and newer CLB architectures, where a local reset can
187
    --      reduce the usability of the slice registers, due to the need to share the control
188
    --      set (RESET/PRESET, CLOCK ENABLE and CLOCK) by all 8 registers in a slice.
189
    --      By using GSR for the initialization, and reducing RESET local init to the bare
190
    --      essential, the model achieves better LUT/FF packing and CLB usability.
191 12 jdoin
    ------------------------------------------------------------------------------------------
192 13 jdoin
    -- internal state signals for register and combinatorial stages
193 12 jdoin
    signal state_next : natural range N downto 0 := 0;      -- state 0 is idle state
194
    signal state_reg : natural range N downto 0 := 0;       -- state 0 is idle state
195 13 jdoin
    -- shifter signals for register and combinatorial stages
196
    signal sh_next : std_logic_vector (N-1 downto 0);
197
    signal sh_reg : std_logic_vector (N-1 downto 0);
198 12 jdoin
    -- mosi and miso connections
199 13 jdoin
    signal rx_bit_next : std_logic;
200
    signal tx_bit_next : std_logic;
201
    signal tx_bit_reg : std_logic;
202
    -- buffered di_i data signals for register and combinatorial stages
203 12 jdoin
    signal di_reg : std_logic_vector (N-1 downto 0);
204 13 jdoin
    -- internal wren_i stretcher for fsm combinatorial stage
205 12 jdoin
    signal wren : std_logic;
206
    signal wr_ack_next : std_logic := '0';
207
    signal wr_ack_reg : std_logic := '0';
208 13 jdoin
    -- buffered do_o data signals for register and combinatorial stages
209
    signal do_buffer_next : std_logic_vector (N-1 downto 0);
210
    signal do_buffer_reg : std_logic_vector (N-1 downto 0);
211 10 jdoin
    -- internal signal to flag transfer to do_buffer_reg
212
    signal do_transfer_next : std_logic := '0';
213
    signal do_transfer_reg : std_logic := '0';
214
    -- internal input data request signal 
215 12 jdoin
    signal di_req_next : std_logic := '0';
216
    signal di_req_reg : std_logic := '0';
217 10 jdoin
    -- cross-clock do_valid_o logic
218
    signal do_valid_next : std_logic := '0';
219
    signal do_valid_A : std_logic := '0';
220
    signal do_valid_B : std_logic := '0';
221
    signal do_valid_C : std_logic := '0';
222
    signal do_valid_D : std_logic := '0';
223
    signal do_valid_o_reg : std_logic := '0';
224
    -- cross-clock di_req_o logic
225
    signal di_req_o_next : std_logic := '0';
226
    signal di_req_o_A : std_logic := '0';
227
    signal di_req_o_B : std_logic := '0';
228
    signal di_req_o_C : std_logic := '0';
229
    signal di_req_o_D : std_logic := '0';
230
    signal di_req_o_reg : std_logic := '0';
231
begin
232
    --=============================================================================================
233
    --  GENERICS CONSTRAINTS CHECKING
234
    --=============================================================================================
235
    -- minimum word width is 8 bits
236
    assert N >= 8
237
    report "Generic parameter 'N' error: SPI shift register size needs to be 8 bits minimum"
238
    severity FAILURE;
239
    -- maximum prefetch lookahead check
240
    assert PREFETCH <= N-5
241
    report "Generic parameter 'PREFETCH' error: lookahead count out of range, needs to be N-5 maximum"
242
    severity FAILURE;
243
 
244
    --=============================================================================================
245 12 jdoin
    --  GENERATE BLOCKS
246 10 jdoin
    --=============================================================================================
247
 
248
    --=============================================================================================
249 12 jdoin
    --  DATA INPUTS
250 10 jdoin
    --=============================================================================================
251 12 jdoin
    -- connect rx bit input
252
    rx_bit_proc : rx_bit_next <= spi_mosi_i;
253 10 jdoin
 
254
    --=============================================================================================
255
    --  CROSS-CLOCK PIPELINE TRANSFER LOGIC
256
    --=============================================================================================
257
    -- do_valid_o and di_req_o strobe output logic
258
    -- this is a delayed pulse generator with a ripple-transfer FFD pipeline, that generates a 
259
    -- fixed-length delayed pulse for the output flags, at the parallel clock domain
260 12 jdoin
    out_transfer_proc : process ( clk_i, do_transfer_reg, di_req_reg,
261 10 jdoin
                                  do_valid_A, do_valid_B, do_valid_D,
262
                                  di_req_o_A, di_req_o_B, di_req_o_D) is
263
    begin
264
        if clk_i'event and clk_i = '1' then                     -- clock at parallel port clock
265
            -- do_transfer_reg -> do_valid_o_reg
266
            do_valid_A <= do_transfer_reg;                      -- the input signal must be at least 2 clocks long
267
            do_valid_B <= do_valid_A;                           -- feed it to a ripple chain of FFDs
268
            do_valid_C <= do_valid_B;
269
            do_valid_D <= do_valid_C;
270
            do_valid_o_reg <= do_valid_next;                    -- registered output pulse
271
            --------------------------------
272 12 jdoin
            -- di_req_reg -> di_req_o_reg
273
            di_req_o_A <= di_req_reg;                           -- the input signal must be at least 2 clocks long
274 10 jdoin
            di_req_o_B <= di_req_o_A;                           -- feed it to a ripple chain of FFDs
275
            di_req_o_C <= di_req_o_B;
276
            di_req_o_D <= di_req_o_C;
277
            di_req_o_reg <= di_req_o_next;                      -- registered output pulse
278
        end if;
279
        -- generate a 2-clocks pulse at the 3rd clock cycle
280
        do_valid_next <= do_valid_A and do_valid_B and not do_valid_D;
281
        di_req_o_next <= di_req_o_A and di_req_o_B and not di_req_o_D;
282
    end process out_transfer_proc;
283
    -- parallel load input registers: data register and write enable
284 12 jdoin
    in_transfer_proc: process (clk_i, wren_i, wr_ack_reg) is
285 10 jdoin
    begin
286
        -- registered data input, input register with clock enable
287
        if clk_i'event and clk_i = '1' then
288
            if wren_i = '1' then
289
                di_reg <= di_i;                                 -- parallel data input buffer register
290
            end if;
291
        end  if;
292
        -- stretch wren pulse to be detected by spi fsm (ffd with sync preset and sync reset)
293
        if clk_i'event and clk_i = '1' then
294
            if wren_i = '1' then                                -- wren_i is the sync preset for wren
295
                wren <= '1';
296 12 jdoin
            elsif wr_ack_reg = '1' then                         -- wr_ack is the sync reset for wren
297 10 jdoin
                wren <= '0';
298
            end if;
299
        end  if;
300
    end process in_transfer_proc;
301
 
302
    --=============================================================================================
303 13 jdoin
    --  REGISTER TRANSFER PROCESSES
304 12 jdoin
    --=============================================================================================
305
    -- fsm state and data registers change on spi SHIFT_EDGE
306
    core_reg_proc : process (spi_sck_i, spi_ssel_i) is
307
    begin
308
        -- FFD registers clocked on SHIFT edge and cleared on idle (spi_ssel_i = 1)
309
        if spi_ssel_i = '1' then                                -- async clr
310
            state_reg <= 0;                                     -- state falls back to idle when slave not selected
311
        elsif spi_sck_i'event and spi_sck_i = SHIFT_EDGE then   -- on SHIFT edge, update all core registers
312
            state_reg <= state_next;                            -- core fsm changes state with spi SHIFT clock
313
        end if;
314
        -- FFD registers clocked on SHIFT edge
315
        if spi_sck_i'event and spi_sck_i = SHIFT_EDGE then      -- on fsm state change, update all core registers
316
            sh_reg <= sh_next;                                  -- core shift register
317
            do_buffer_reg <= do_buffer_next;                    -- registered data output
318
            do_transfer_reg <= do_transfer_next;                -- cross-clock transfer flag
319
            di_req_reg <= di_req_next;                          -- input data request
320
            wr_ack_reg <= wr_ack_next;                          -- wren ack for data load synchronization
321
        end if;
322
        -- FFD registers clocked on CHANGE edge
323
        if spi_sck_i'event and spi_sck_i = CHANGE_EDGE then
324
            tx_bit_reg <= tx_bit_next;                          -- update MISO driver from the MSb
325
        end if;
326
    end process core_reg_proc;
327
 
328
    --=============================================================================================
329 13 jdoin
    --  COMBINATORIAL LOGIC PROCESSES
330 10 jdoin
    --=============================================================================================
331 13 jdoin
    -- state and datapath combinatorial logic
332 12 jdoin
    core_combi_proc : process ( sh_reg, sh_next, state_reg, tx_bit_reg, rx_bit_next, do_buffer_reg,
333
                                do_transfer_reg, di_reg, di_req_reg, wren, wr_ack_reg) is
334 10 jdoin
    begin
335 12 jdoin
        -- all output signals are assigned to (avoid latches)
336
        sh_next <= sh_reg;                                              -- shift register
337
        tx_bit_next <= tx_bit_reg;                                      -- MISO driver
338 10 jdoin
        do_buffer_next <= do_buffer_reg;                                -- output data buffer
339
        do_transfer_next <= do_transfer_reg;                            -- output data flag
340 12 jdoin
        wr_ack_next <= wr_ack_reg;                                      -- write enable acknowledge
341
        di_req_next <= di_req_reg;                                      -- data input request
342
        state_next <= state_reg;                                        -- fsm control state
343 10 jdoin
        case state_reg is
344 13 jdoin
 
345 16 jdoin
            when (N) =>                                                 -- deassert 'di_rdy' and stretch do_valid
346 13 jdoin
                wr_ack_next <= '0';                                     -- acknowledge data in transfer
347 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
348
                tx_bit_next <= sh_reg(N-1);                             -- output next MSbit
349 10 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
350 12 jdoin
                sh_next(0) <= rx_bit_next;                              -- shift in rx bit into LSb
351
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
352 13 jdoin
 
353 16 jdoin
            when (N-1) downto (PREFETCH+3) =>                           -- remove 'do_transfer' and shift bits
354
                do_transfer_next <= '0';                                -- reset 'do_valid' transfer signal
355 12 jdoin
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
356
                wr_ack_next <= '0';                                     -- remove data load ack for all but the load stages
357
                tx_bit_next <= sh_reg(N-1);                             -- output next MSbit
358 10 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
359 12 jdoin
                sh_next(0) <= rx_bit_next;                              -- shift in rx bit into LSb
360
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
361 13 jdoin
 
362 16 jdoin
            when (PREFETCH+2) downto 3 =>                               -- raise prefetch 'di_req_o' signal
363 12 jdoin
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
364
                wr_ack_next <= '0';                                     -- remove data load ack for all but the load stages
365
                tx_bit_next <= sh_reg(N-1);                             -- output next MSbit
366 10 jdoin
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
367 12 jdoin
                sh_next(0) <= rx_bit_next;                              -- shift in rx bit into LSb
368
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
369 13 jdoin
 
370 16 jdoin
            when 2 =>                                                   -- transfer received data to do_buffer_reg on next cycle
371 12 jdoin
                di_req_next <= '1';                                     -- request data in advance to allow for pipeline delays
372
                wr_ack_next <= '0';                                     -- remove data load ack for all but the load stages
373
                tx_bit_next <= sh_reg(N-1);                             -- output next MSbit
374
                sh_next(N-1 downto 1) <= sh_reg(N-2 downto 0);          -- shift inner bits
375
                sh_next(0) <= rx_bit_next;                              -- shift in rx bit into LSb
376
                do_transfer_next <= '1';                                -- signal transfer to do_buffer on next cycle
377
                do_buffer_next <= sh_next;                              -- get next data directly into rx buffer
378
                state_next <= state_reg - 1;                            -- update next state at each sck pulse
379 13 jdoin
 
380 16 jdoin
            when 1 =>                                                   -- transfer rx data to do_buffer and restart if new data is written
381 12 jdoin
                sh_next(0) <= rx_bit_next;                              -- shift in rx bit into LSb
382
                sh_next(N-1 downto 1) <= di_reg(N-2 downto 0);          -- shift inner bits
383
                tx_bit_next <= di_reg(N-1);                             -- first output bit comes from the MSb of parallel data
384
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
385 18 jdoin
                state_next <= N;                                            -- next state is top bit of new data
386 10 jdoin
                if wren = '1' then                                      -- load tx register if valid data present at di_reg
387 12 jdoin
                    wr_ack_next <= '1';                                 -- acknowledge data in transfer
388 10 jdoin
                else
389 12 jdoin
                    wr_ack_next <= '0';                                 -- remove data load ack for all but the load stages
390 10 jdoin
                end if;
391 13 jdoin
 
392 16 jdoin
            when 0 =>                                                   -- idle state: start and end of transmission
393 13 jdoin
                sh_next(0) <= rx_bit_next;                              -- shift in rx bit into LSb
394
                sh_next(N-1 downto 1) <= di_reg(N-2 downto 0);          -- shift inner bits
395
                wr_ack_next <= '1';                                     -- acknowledge data in transfer
396
                di_req_next <= '0';                                     -- prefetch data request: deassert when shifting data
397 12 jdoin
                do_transfer_next <= '0';                                -- clear signal transfer to do_buffer
398
                tx_bit_next <= di_reg(N-1);                             -- first output bit comes from the MSb of parallel data
399
                state_next <= N;                                        -- next state is top bit of new data
400 13 jdoin
 
401 10 jdoin
            when others =>
402 12 jdoin
                state_next <= 0;                                        -- safe state
403 13 jdoin
 
404 10 jdoin
        end case;
405
    end process core_combi_proc;
406
 
407
    --=============================================================================================
408 13 jdoin
    --  OUTPUT LOGIC PROCESSES
409 10 jdoin
    --=============================================================================================
410
    -- data output processes
411 12 jdoin
    do_o_proc :         do_o <= do_buffer_reg;                          -- do_o always available
412
    do_valid_o_proc:    do_valid_o <= do_valid_o_reg;                   -- copy registered do_valid_o to output
413
    di_req_o_proc:      di_req_o <= di_req_o_reg;                       -- copy registered di_req_o to output
414
    wr_ack_o_proc:      wr_ack_o <= wr_ack_reg;                         -- copy registered wr_ack_o to output
415 10 jdoin
 
416 13 jdoin
    -----------------------------------------------------------------------------------------------
417
    -- MISO driver process: copy next tx bit at reset
418
    -----------------------------------------------------------------------------------------------
419
    -- this is a MUX that selects the combinatorial next tx bit at reset, and the registered tx bit
420
    -- at sequential operation. The mux gives us a preload of the first bit, simplifying the shifter logic.
421
    spi_miso_o_proc: process (spi_ssel_i, tx_bit_reg, tx_bit_next) is
422
    begin
423
        if spi_ssel_i = '1' then
424
            spi_miso_o <= tx_bit_next;                                  -- copy next => reg at reset
425
        else
426
            spi_miso_o <= tx_bit_reg;
427
        end if;
428
    end process spi_miso_o_proc;
429
 
430 10 jdoin
    --=============================================================================================
431
    --  DEBUG LOGIC PROCESSES
432
    --=============================================================================================
433 13 jdoin
    -- these signals are useful for verification, and can be deleted after debug.
434 10 jdoin
    do_transfer_proc:   do_transfer_o <= do_transfer_reg;
435 13 jdoin
    state_debug_proc:   state_dbg_o <= std_logic_vector(to_unsigned(state_reg, 4)); -- export internal state to debug
436 12 jdoin
    rx_bit_next_proc:   rx_bit_next_o <= rx_bit_next;
437 10 jdoin
    wren_o_proc:        wren_o <= wren;
438
    sh_reg_debug_proc:  sh_reg_dbg_o <= sh_reg;                                     -- export sh_reg to debug
439 13 jdoin
end architecture rtl;
440 10 jdoin
 

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