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////////////////////////////////////////////////////////////////// ////
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//// ////
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//// SPI SLAVE IP Core ////
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//// ////
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//// This file is part of the spislave project ////
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//// http://www.opencores.org/project,spislave ////
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//// ////
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//// Description ////
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//// Implementation of spislave IP core according to ////
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//// spislave IP core specification document. ////
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//// ////
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//// To Do: ////
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//// - ////
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//// ////
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//// Author(s): ////
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//// - Sivakumar.B , email: siva@zilogic.com ////
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//// email: siva12@opencores.org ////
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//// Engineer Zilogic systems,chennai. www.zilogic.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009 Zilogic Systems and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// RTL program for SPI GPIO -- shift 8 bit register ////
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siva12 |
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`define P0_P9_OP 8'b10101010 //0xAA
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`define P0_P3_OP 8'b11111111 //0xFF
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`define P4_P7_OP 8'b11111110 //0xFE
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module spigpio(clk, cs, sr_in, gpioout, sr_out);
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input clk, cs;
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input sr_in;
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output sr_out;
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output [7:0] gpioout;
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reg [7:0] gpioout;
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reg sr_out;
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wire rw;
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reg [7:0] sr;
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assign rw = sr[7];
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always@(posedge clk )
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begin
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if (cs == 1'b0)
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begin
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sr_out <= sr[7];
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sr[7:1] <= sr[6:0];
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sr[0] <= sr_in;
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end
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if (cs == 1'b1)
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begin
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if (rw == 1'b1)
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begin
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case (sr)
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`P0_P9_OP : gpioout[7:0] <= { sr[0], sr[1], sr[2], sr[3],
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sr[4], sr[5], sr[6], sr[7]};
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`P0_P3_OP : gpioout[3:0] <= {sr[0], sr[1], sr[2], sr[3]};
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`P4_P7_OP : gpioout[7:4] <= { sr[4], sr[5], sr[6], sr[7]};
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default : gpioout[0] <= sr[0];
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endcase
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end
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end
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end
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endmodule
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