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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [common/] [sd_seq_check.v] - Blame information for rev 22

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1 3 ghutchis 
//----------------------------------------------------------------------
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// Srdy/Drdy sequence checker
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//
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// Simplistic traffic checker for srdy/drdy blocks.  Checks for an
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// incrementing data sequence.
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//
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// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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// Author: Guy Hutchison
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//
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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 `define SDLIB_DELAY #1
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`endif
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module sd_seq_check
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  #(parameter width=8)
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  (input clk,
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   input reset,
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   input          c_srdy,
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   output reg     c_drdy,
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   input [width-1:0] c_data);
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  parameter pat_dep = 8;
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  reg [width-1:0]    last_seq;
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  reg                first;
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  reg [pat_dep-1:0]  drdy_pat;
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  integer            dpp;
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  reg                nxt_c_drdy;
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  integer            err_cnt;
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  initial
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    begin
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      drdy_pat = {pat_dep{1'b1}};
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      dpp = 0;
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    end
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  initial
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    begin
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      first = 1;
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      c_drdy = 0;
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      err_cnt = 0;
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    end
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  always @*
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    begin
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      nxt_c_drdy = c_drdy;
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      if (c_srdy & c_drdy)
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        begin
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          if (drdy_pat[dpp])
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            begin
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              nxt_c_drdy = 1;
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            end
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          else
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            nxt_c_drdy = 0;
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        end
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      else if (!c_drdy)
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        begin
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          if (drdy_pat[dpp])
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            begin
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              nxt_c_drdy = 1;
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            end
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          else
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            nxt_c_drdy = 0;
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        end
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    end
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  always @(posedge clk)
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    begin
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      if ((c_srdy & c_drdy) | !c_drdy)
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        dpp = (dpp + 1) % pat_dep;
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    end
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  always @(posedge clk)
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    begin
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      if (reset)
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        begin
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          c_drdy <= `SDLIB_DELAY 0;
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          err_cnt  = 0;
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          drdy_pat = {pat_dep{1'b1}};
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          dpp = 0;
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          first = 1;
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          last_seq = 0;
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        end
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      else
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        begin
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          c_drdy <= `SDLIB_DELAY nxt_c_drdy;
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          if (c_srdy & c_drdy)
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            begin
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              if (!first && (c_data !== (last_seq + 1)))
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                begin
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                  $display ("%t: ERROR   : %m: Sequence miscompare rcv=%x exp=%x",
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                            $time, c_data, last_seq+1);
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                  err_cnt = err_cnt + 1;
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                end
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              else
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                begin
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                  last_seq = c_data;
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                  first = 0;
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                end
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            end // if (c_srdy & c_drdy)
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        end // else: !if(reset)
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    end
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endmodule // sd_seq_check

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