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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [common/] [sd_seq_gen.v] - Blame information for rev 22

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//----------------------------------------------------------------------
// Srdy/Drdy sequence generator
//
// Simplistic traffic generator for srdy/drdy blocks.  Generates an
// incrementing data sequence.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_seq_gen
  #(parameter width=8)
  (input clk,
   input reset,
   output reg     p_srdy,
   input          p_drdy,
   output reg [width-1:0] p_data);
 
  reg                     nxt_p_srdy;
  reg [width-1:0]          nxt_p_data;
 
  parameter pat_dep = 8;
 
  reg [pat_dep-1:0]        srdy_pat;
  integer                 spp, startup;
  integer                 rep_count;
 
  initial
    begin
      srdy_pat = {pat_dep{1'b1}};
      spp = 0;
      startup = 0;
      rep_count = 0;
    end
 
  always @*
    begin
      nxt_p_data = p_data;
      nxt_p_srdy = p_srdy;
 
      if (p_srdy & p_drdy)
        begin
 
          if (srdy_pat[spp] && (rep_count > 1))
            begin
              nxt_p_data = p_data + 1;
              nxt_p_srdy = 1;
            end
          else
            nxt_p_srdy = 0;
        end // if (p_srdy & p_drdy)
      else if (!p_srdy && (rep_count != 0))
        begin
          if (srdy_pat[spp])
            begin
              nxt_p_data = p_data + 1;
              nxt_p_srdy = 1;
            end
          else
            nxt_p_srdy = 0;
        end
    end // always @ *
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          srdy_pat = {pat_dep{1'b1}};
          spp = 0;
          startup = 0;
          rep_count = 0;
        end
      else
        begin
          if ((p_srdy & p_drdy) | !p_srdy)
            spp = (spp + 1) % pat_dep;
 
          if (p_srdy & p_drdy)
            begin
              if (rep_count != -1)
                rep_count = rep_count - 1;
            end
        end
    end
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          p_srdy <= `SDLIB_DELAY 0;
          p_data <= `SDLIB_DELAY 0;
        end
      else
        begin
          p_srdy <= `SDLIB_DELAY nxt_p_srdy;
          p_data <= `SDLIB_DELAY nxt_p_data;
        end
    end // always @ (posedge clk)
 
  // simple blocking task to send N words and then wait until complete
  task send;
    input [31:0] amount;
    begin
      rep_count = amount;
      @(posedge clk);
      while (rep_count != 0)
        @(posedge clk);
    end
  endtask
 
endmodule // sd_seq_gen

Line No.	Rev	Author	Line
1	3	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy sequence generator`
3			`//`
4			`// Simplistic traffic generator for srdy/drdy blocks. Generates an`
5			`// incrementing data sequence.`
6			`//`
7			`// Naming convention: c = consumer, p = producer, i = internal interface`
8			`//----------------------------------------------------------------------`
9			`// Author: Guy Hutchison`
10			`//`
11			`// This block is uncopyrighted and released into the public domain.`
12			`//----------------------------------------------------------------------`
13
14			`// delay unit for nonblocking assigns, default is to #1`
15			`ifndef SDLIB_DELAY
16			`define SDLIB_DELAY #1
17			`endif
18
19			`module sd_seq_gen`
20			`#(parameter width=8)`
21			`(input clk,`
22			`input reset,`
23			`output reg p_srdy,`
24			`input p_drdy,`
25			`output reg [width-1:0] p_data);`
26
27			`reg nxt_p_srdy;`
28			`reg [width-1:0] nxt_p_data;`
29
30			`parameter pat_dep = 8;`
31
32			`reg [pat_dep-1:0] srdy_pat;`
33			`integer spp, startup;`
34	14	ghutchis	`integer rep_count;`
35	3	ghutchis
36			`initial`
37			`begin`
38			`srdy_pat = {pat_dep{1'b1}};`
39			`spp = 0;`
40			`startup = 0;`
41	14	ghutchis	`rep_count = 0;`
42	3	ghutchis	`end`
43
44			`always @*`
45			`begin`
46			`nxt_p_data = p_data;`
47			`nxt_p_srdy = p_srdy;`
48
49	14	ghutchis	`if (p_srdy & p_drdy)`
50	3	ghutchis	`begin`
51	14	ghutchis
52			`if (srdy_pat[spp] && (rep_count > 1))`
53	3	ghutchis	`begin`
54			`nxt_p_data = p_data + 1;`
55			`nxt_p_srdy = 1;`
56			`end`
57			`else`
58			`nxt_p_srdy = 0;`
59	14	ghutchis	`end // if (p_srdy & p_drdy)`
60			`else if (!p_srdy && (rep_count != 0))`
61	3	ghutchis	`begin`
62			`if (srdy_pat[spp])`
63			`begin`
64			`nxt_p_data = p_data + 1;`
65			`nxt_p_srdy = 1;`
66			`end`
67			`else`
68			`nxt_p_srdy = 0;`
69			`end`
70			`end // always @ *`
71
72			`always @(posedge clk)`
73			`begin`
74	22	ghutchis	`if (reset)`
75			`begin`
76			`srdy_pat = {pat_dep{1'b1}};`
77			`spp = 0;`
78			`startup = 0;`
79			`rep_count = 0;`
80			`end`
81			`else`
82			`begin`
83			`if ((p_srdy & p_drdy) \| !p_srdy)`
84			`spp = (spp + 1) % pat_dep;`
85
86			`if (p_srdy & p_drdy)`
87			`begin`
88			`if (rep_count != -1)`
89			`rep_count = rep_count - 1;`
90			`end`
91			`end`
92	3	ghutchis	`end`
93
94			`always @(posedge clk)`
95			`begin`
96			`if (reset)`
97			`begin`
98			p_srdy <= `SDLIB_DELAY 0;
99			p_data <= `SDLIB_DELAY 0;
100			`end`
101			`else`
102			`begin`
103			p_srdy <= `SDLIB_DELAY nxt_p_srdy;
104			p_data <= `SDLIB_DELAY nxt_p_data;
105			`end`
106	14	ghutchis	`end // always @ (posedge clk)`
107
108			`// simple blocking task to send N words and then wait until complete`
109			`task send;`
110			`input [31:0] amount;`
111			`begin`
112			`rep_count = amount;`
113			`@(posedge clk);`
114			`while (rep_count != 0)`
115			`@(posedge clk);`
116	3	ghutchis	`end`
117	14	ghutchis	`endtask`
118	3	ghutchis
119			`endmodule // sd_seq_gen`

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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [common/] [sd_seq_gen.v] - Blame information for rev 22