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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [scoreboard/] [sb_driver.v] - Blame information for rev 18

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//----------------------------------------------------------------------
// Srdy/Drdy sequence generator
//
// Simplistic traffic generator for srdy/drdy blocks.  Generates an
// incrementing data sequence.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sb_driver
  #(parameter width=8,
    parameter items=64,
    parameter use_txid=0,
    parameter use_mask=0,
    parameter txid_sz=2,
    parameter asz=$clog2(items))
  (input clk,
   input reset,
   output reg     p_srdy,
   input          p_drdy,
   output reg      p_req_type, // 0=read, 1=write
   output reg [txid_sz-1:0] p_txid,
   output reg [width-1:0] p_mask,
   output reg [asz-1:0]   p_itemid,
   output reg [width-1:0] p_data);
 
/* -----\/----- EXCLUDED -----\/-----
  parameter pat_dep = 8;
 
  reg [pat_dep-1:0]       srdy_pat;
  integer                 spp, startup;
  integer                 rep_count;
 
  initial
    begin
      srdy_pat = {pat_dep{1'b1}};
      spp = 0;
      startup = 0;
      rep_count = 0;
    end
 
  always @*
    begin
      nxt_p_data = p_data;
      nxt_p_srdy = p_srdy;
      nxt_p_req_type = p_req_type;
 
      if (p_srdy & p_drdy)
        begin
 
          if (srdy_pat[spp] && (rep_count > 1))
            begin
              nxt_p_data = p_data + 1;
              nxt_p_srdy = 1;
            end
          else
            nxt_p_srdy = 0;
        end // if (p_srdy & p_drdy)
      else if (!p_srdy && (rep_count != 0))
        begin
          if (srdy_pat[spp])
            begin
              nxt_p_data = p_data + 1;
              nxt_p_srdy = 1;
            end
          else
            nxt_p_srdy = 0;
        end
    end // always @ *
 
  always @(posedge clk)
    begin
      if ((p_srdy & p_drdy) | !p_srdy)
        spp = (spp + 1) % pat_dep;
 
      if (p_srdy & p_drdy)
        begin
          if (rep_count != -1)
            rep_count = rep_count - 1;
        end
    end
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          p_srdy <= `SDLIB_DELAY 0;
          p_data <= `SDLIB_DELAY 0;
        end
      else
        begin
          p_srdy <= `SDLIB_DELAY nxt_p_srdy;
          p_data <= `SDLIB_DELAY nxt_p_data;
        end
    end // always @ (posedge clk)
 -----/\----- EXCLUDED -----/\----- */
 
  initial
    begin
      p_srdy <= #1 0;
      p_req_type <= #1 0;
      p_txid <= #1 0;
      p_mask <= #1 0;
      p_itemid <= #1 0;
      p_data <= #1 0;
    end
 
 
  task send;
    input req_type;
    //input [txid_sz-1:0] txid;
    input [width-1:0]   mask;
    input [width-1:0]   data;
    input [asz-1:0]     itemid;
    begin
      p_srdy <= #1 1;
   //input          p_drdy,
      p_req_type <= #1 req_type;
      p_txid <= #1 itemid;
      p_mask <= #1 mask;
      p_itemid <= #1 itemid;
      p_data <= #1 data;
      @(negedge clk);
      if (p_drdy)
        begin
          @(posedge clk);
          p_srdy <= #1 0;
        end
      else
        begin
          while (!p_drdy)
            @(posedge clk);
          p_srdy <= #1 0;
        end
    end
  endtask
 
endmodule // sb_driver

Line No.	Rev	Author	Line
1	18	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy sequence generator`
3			`//`
4			`// Simplistic traffic generator for srdy/drdy blocks. Generates an`
5			`// incrementing data sequence.`
6			`//`
7			`// Naming convention: c = consumer, p = producer, i = internal interface`
8			`//----------------------------------------------------------------------`
9			`// Author: Guy Hutchison`
10			`//`
11			`// This block is uncopyrighted and released into the public domain.`
12			`//----------------------------------------------------------------------`
13
14			`// delay unit for nonblocking assigns, default is to #1`
15			`ifndef SDLIB_DELAY
16			`define SDLIB_DELAY #1
17			`endif
18
19			`module sb_driver`
20			`#(parameter width=8,`
21			`parameter items=64,`
22			`parameter use_txid=0,`
23			`parameter use_mask=0,`
24			`parameter txid_sz=2,`
25			`parameter asz=$clog2(items))`
26			`(input clk,`
27			`input reset,`
28			`output reg p_srdy,`
29			`input p_drdy,`
30			`output reg p_req_type, // 0=read, 1=write`
31			`output reg [txid_sz-1:0] p_txid,`
32			`output reg [width-1:0] p_mask,`
33			`output reg [asz-1:0] p_itemid,`
34			`output reg [width-1:0] p_data);`
35
36			`/* -----\/----- EXCLUDED -----\/-----`
37			`parameter pat_dep = 8;`
38
39			`reg [pat_dep-1:0] srdy_pat;`
40			`integer spp, startup;`
41			`integer rep_count;`
42
43			`initial`
44			`begin`
45			`srdy_pat = {pat_dep{1'b1}};`
46			`spp = 0;`
47			`startup = 0;`
48			`rep_count = 0;`
49			`end`
50
51			`always @*`
52			`begin`
53			`nxt_p_data = p_data;`
54			`nxt_p_srdy = p_srdy;`
55			`nxt_p_req_type = p_req_type;`
56
57			`if (p_srdy & p_drdy)`
58			`begin`
59
60			`if (srdy_pat[spp] && (rep_count > 1))`
61			`begin`
62			`nxt_p_data = p_data + 1;`
63			`nxt_p_srdy = 1;`
64			`end`
65			`else`
66			`nxt_p_srdy = 0;`
67			`end // if (p_srdy & p_drdy)`
68			`else if (!p_srdy && (rep_count != 0))`
69			`begin`
70			`if (srdy_pat[spp])`
71			`begin`
72			`nxt_p_data = p_data + 1;`
73			`nxt_p_srdy = 1;`
74			`end`
75			`else`
76			`nxt_p_srdy = 0;`
77			`end`
78			`end // always @ *`
79
80			`always @(posedge clk)`
81			`begin`
82			`if ((p_srdy & p_drdy) \| !p_srdy)`
83			`spp = (spp + 1) % pat_dep;`
84
85			`if (p_srdy & p_drdy)`
86			`begin`
87			`if (rep_count != -1)`
88			`rep_count = rep_count - 1;`
89			`end`
90			`end`
91
92			`always @(posedge clk)`
93			`begin`
94			`if (reset)`
95			`begin`
96			p_srdy <= `SDLIB_DELAY 0;
97			p_data <= `SDLIB_DELAY 0;
98			`end`
99			`else`
100			`begin`
101			p_srdy <= `SDLIB_DELAY nxt_p_srdy;
102			p_data <= `SDLIB_DELAY nxt_p_data;
103			`end`
104			`end // always @ (posedge clk)`
105			`-----/\----- EXCLUDED -----/\----- */`
106
107			`initial`
108			`begin`
109			`p_srdy <= #1 0;`
110			`p_req_type <= #1 0;`
111			`p_txid <= #1 0;`
112			`p_mask <= #1 0;`
113			`p_itemid <= #1 0;`
114			`p_data <= #1 0;`
115			`end`
116
117
118			`task send;`
119			`input req_type;`
120			`//input [txid_sz-1:0] txid;`
121			`input [width-1:0] mask;`
122			`input [width-1:0] data;`
123			`input [asz-1:0] itemid;`
124			`begin`
125			`p_srdy <= #1 1;`
126			`//input p_drdy,`
127			`p_req_type <= #1 req_type;`
128			`p_txid <= #1 itemid;`
129			`p_mask <= #1 mask;`
130			`p_itemid <= #1 itemid;`
131			`p_data <= #1 data;`
132			`@(negedge clk);`
133			`if (p_drdy)`
134			`begin`
135			`@(posedge clk);`
136			`p_srdy <= #1 0;`
137			`end`
138			`else`
139			`begin`
140			`while (!p_drdy)`
141			`@(posedge clk);`
142			`p_srdy <= #1 0;`
143			`end`
144			`end`
145			`endtask`
146
147			`endmodule // sb_driver`

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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [scoreboard/] [sb_driver.v] - Blame information for rev 18