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[/] [srdydrdy_lib/] [trunk/] [env/] [verilog/] [scoreboard/] [sb_monitor.v] - Blame information for rev 18

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1 18 ghutchis 
// combination refmodel/monitor for scoreboard
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module sb_monitor
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  #(parameter width=8,
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    parameter items=64,
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    parameter use_txid=0,
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    parameter use_mask=0,
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    parameter txid_sz=2,
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    parameter asz=$clog2(items))
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  (input      clk,
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   input      reset,
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   input      c_srdy,
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   input      c_drdy,
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   input      c_req_type, // 0=read, 1=write
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   input [txid_sz-1:0] c_txid,
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   input [width-1:0] c_mask,
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   input [width-1:0] c_data,
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   input [asz-1:0]   c_itemid,
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   input     p_srdy,
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   output reg   p_drdy,
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   input  [txid_sz-1:0] p_txid,
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   input [width-1:0]   p_data
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   );
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  reg [width-1:0]      sbmem [0:items-1];
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  always @(posedge clk)
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    begin
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      if (c_srdy & c_drdy & (c_req_type == 1))
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        begin
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          sbmem[c_itemid] <= #20 (sbmem[c_itemid] & ~c_mask) | (c_data & c_mask);
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        end
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      if (p_srdy & p_drdy)
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        begin
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          if (p_data != sbmem[p_txid])
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            begin
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              $display ("%t: ERROR: sb returned %x, expected %x",
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                        $time, p_data, sbmem[p_txid]);
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            end
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        end
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    end
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  initial
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    begin
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      p_drdy = 1;
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    end
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endmodule // sb_monitor

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