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module port_macro
  #(parameter port_num = 0)
  (input         clk,
   input         reset,
 
   input [`PRW_SZ-1:0]   ri_data,                // To ring_tap of port_ring_tap.v
   output [`PRW_SZ-1:0]  ro_data,                // From ring_tap of port_ring_tap.v
   input [`NUM_PORTS-1:0] fli_data,              // To ring_tap of port_ring_tap.v
   /*AUTOINPUT*/
   // Beginning of automatic inputs (from unused autoinst inputs)
   input                fli_srdy,               // To ring_tap of port_ring_tap.v
   input                gmii_rx_clk,            // To port_clocking of port_clocking.v, ...
   input                gmii_rx_dv,             // To rx_gigmac of sd_rx_gigmac.v
   input [7:0]          gmii_rxd,               // To rx_gigmac of sd_rx_gigmac.v
   input                p2f_drdy,               // To pkt_parse of pkt_parse.v
   input                rarb_ack,               // To ring_tap of port_ring_tap.v
   input                ri_srdy,                // To ring_tap of port_ring_tap.v
   input                ro_drdy,                // To ring_tap of port_ring_tap.v
   // End of automatics
 
   output               rarb_req,
   output               fli_drdy,               // From ring_tap of port_ring_tap.v
   output               gmii_tx_en,             // From tx_gmii of sd_tx_gigmac.v
   output [7:0]          gmii_txd,               // From tx_gmii of sd_tx_gigmac.v
   output [`PAR_DATA_SZ-1:0] p2f_data,           // From pkt_parse of pkt_parse.v
   output               p2f_srdy,               // From pkt_parse of pkt_parse.v
   output               ri_drdy,                // From ring_tap of port_ring_tap.v
   output               ro_srdy                 // From ring_tap of port_ring_tap.v
   );
 
  wire [`RX_USG_SZ-1:0] rx_usage;
  wire [`TX_USG_SZ-1:0] tx_usage;
  wire [`PFW_SZ-1:0]     prx_data;               // From fifo_rx of sd_fifo_b.v
  wire [`PFW_SZ-1:0]     ptx_data;               // From fifo_tx of sd_fifo_b.v
  wire [`PFW_SZ-1:0]     rttx_data;              // From ring_tap of port_ring_tap.v
  wire [1:0]             rxg_code;               // From rx_sync_fifo of sd_fifo_s.v
  wire [7:0]             rxg_data;               // From rx_sync_fifo of sd_fifo_s.v
  wire [`PFW_SZ-1:0]     ctx_data;               // From oflow of egr_oflow.v
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire                  crx_abort;              // From con of concentrator.v
  wire                  crx_commit;             // From con of concentrator.v
  wire [`PFW_SZ-1:0]    crx_data;               // From con of concentrator.v
  wire                  crx_drdy;               // From fifo_rx of sd_fifo_b.v
  wire                  crx_srdy;               // From con of concentrator.v
  wire                  ctx_abort;              // From oflow of egr_oflow.v
  wire                  ctx_commit;             // From oflow of egr_oflow.v
  wire                  ctx_drdy;               // From fifo_tx of sd_fifo_b.v
  wire                  ctx_srdy;               // From oflow of egr_oflow.v
  wire                  gmii_rx_reset;          // From port_clocking of port_clocking.v
  wire [1:0]            pdo_code;               // From pkt_parse of pkt_parse.v
  wire [7:0]            pdo_data;               // From pkt_parse of pkt_parse.v
  wire                  pdo_drdy;               // From con of concentrator.v
  wire                  pdo_srdy;               // From pkt_parse of pkt_parse.v
  wire                  prx_drdy;               // From ring_tap of port_ring_tap.v
  wire                  prx_srdy;               // From fifo_rx of sd_fifo_b.v
  wire                  ptx_drdy;               // From dst of distributor.v
  wire                  ptx_srdy;               // From fifo_tx of sd_fifo_b.v
  wire                  rarb_req;               // From ring_tap of port_ring_tap.v
  wire                  rttx_drdy;              // From oflow of egr_oflow.v
  wire                  rttx_srdy;              // From ring_tap of port_ring_tap.v
  wire [1:0]            rxc_rxg_code;           // From rx_gigmac of sd_rx_gigmac.v
  wire [7:0]            rxc_rxg_data;           // From rx_gigmac of sd_rx_gigmac.v
  wire                  rxc_rxg_drdy;           // From rx_sync_fifo of sd_fifo_s.v
  wire                  rxc_rxg_srdy;           // From rx_gigmac of sd_rx_gigmac.v
  wire                  rxg_drdy;               // From pkt_parse of pkt_parse.v
  wire                  rxg_srdy;               // From rx_sync_fifo of sd_fifo_s.v
  wire [1:0]            txg_code;               // From dst of distributor.v
  wire [7:0]            txg_data;               // From dst of distributor.v
  wire                  txg_drdy;               // From tx_gmii of sd_tx_gigmac.v
  wire                  txg_srdy;               // From dst of distributor.v
  // End of automatics
 
 
  port_clocking port_clocking
    (/*AUTOINST*/
     // Outputs
     .gmii_rx_reset                     (gmii_rx_reset),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .gmii_rx_clk                       (gmii_rx_clk));
 
/*  sd_rx_gigmac AUTO_TEMPLATE
 (
   .clk                         (gmii_rx_clk),
   .reset                       (gmii_rx_reset),
   .rxg_\(.*\)                  (rxc_rxg_\1[]),
 );
 */
  sd_rx_gigmac rx_gigmac
    (/*AUTOINST*/
     // Outputs
     .rxg_srdy                          (rxc_rxg_srdy),          // Templated
     .rxg_code                          (rxc_rxg_code[1:0]),     // Templated
     .rxg_data                          (rxc_rxg_data[7:0]),     // Templated
     // Inputs
     .clk                               (gmii_rx_clk),           // Templated
     .reset                             (gmii_rx_reset),         // Templated
     .gmii_rx_dv                        (gmii_rx_dv),
     .gmii_rxd                          (gmii_rxd[7:0]),
     .rxg_drdy                          (rxc_rxg_drdy));          // Templated
 
/* sd_fifo_s AUTO_TEMPLATE
 (
     .c_clk                             (gmii_rx_clk),
     .c_reset                           (gmii_rx_reset),
     .c_data                            ({rxc_rxg_code,rxc_rxg_data}),
     .p_data                            ({rxg_code,rxg_data}),
     .p_clk                             (clk),
     .p_reset                           (reset),
  .c_\(.*\)                     (rxc_rxg_\1[]),
  .p_\(.*\)                     (rxg_\1[]),
 );
 */
  sd_fifo_s #(8+2,16,1) rx_sync_fifo
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (rxc_rxg_drdy),          // Templated
     .p_srdy                            (rxg_srdy),              // Templated
     .p_data                            ({rxg_code,rxg_data}),   // Templated
     // Inputs
     .c_clk                             (gmii_rx_clk),           // Templated
     .c_reset                           (gmii_rx_reset),         // Templated
     .c_srdy                            (rxc_rxg_srdy),          // Templated
     .c_data                            ({rxc_rxg_code,rxc_rxg_data}), // Templated
     .p_clk                             (clk),                   // Templated
     .p_reset                           (reset),                 // Templated
     .p_drdy                            (rxg_drdy));              // Templated
 
  pkt_parse #(port_num) pkt_parse
    (/*AUTOINST*/
     // Outputs
     .rxg_drdy                          (rxg_drdy),
     .p2f_srdy                          (p2f_srdy),
     .p2f_data                          (p2f_data[`PAR_DATA_SZ-1:0]),
     .pdo_srdy                          (pdo_srdy),
     .pdo_code                          (pdo_code[1:0]),
     .pdo_data                          (pdo_data[7:0]),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .rxg_srdy                          (rxg_srdy),
     .rxg_code                          (rxg_code[1:0]),
     .rxg_data                          (rxg_data[7:0]),
     .p2f_drdy                          (p2f_drdy),
     .pdo_drdy                          (pdo_drdy));
 
/* concentrator AUTO_TEMPLATE
 (
    .c_\(.*\)     (pdo_\1[]),
    .p_\(.*\)     (crx_\1[]),
 );
 */
  concentrator con
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (pdo_drdy),              // Templated
     .p_data                            (crx_data[`PFW_SZ-1:0]), // Templated
     .p_srdy                            (crx_srdy),              // Templated
     .p_commit                          (crx_commit),            // Templated
     .p_abort                           (crx_abort),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_data                            (pdo_data[7:0]),         // Templated
     .c_code                            (pdo_code[1:0]),         // Templated
     .c_srdy                            (pdo_srdy),              // Templated
     .p_drdy                            (crx_drdy));              // Templated
 
  /* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"
   (
    .p_abort  (1'b0),
    .p_commit (1'b0),
    .usage    (@_usage),
    .c_\(.*\)     (c@_\1),
    .p_\(.*\)    (p@_\1),
   );
   */
  sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (crx_drdy),              // Templated
     .p_srdy                            (prx_srdy),              // Templated
     .p_data                            (prx_data),              // Templated
     .usage                             (rx_usage),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (crx_srdy),              // Templated
     .c_commit                          (crx_commit),            // Templated
     .c_abort                           (crx_abort),             // Templated
     .c_data                            (crx_data),              // Templated
     .p_drdy                            (prx_drdy),              // Templated
     .p_commit                          (1'b0),                  // Templated
     .p_abort                           (1'b0));                  // Templated
 
  sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (ctx_drdy),              // Templated
     .p_srdy                            (ptx_srdy),              // Templated
     .p_data                            (ptx_data),              // Templated
     .usage                             (tx_usage),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ctx_srdy),              // Templated
     .c_commit                          (ctx_commit),            // Templated
     .c_abort                           (ctx_abort),             // Templated
     .c_data                            (ctx_data),              // Templated
     .p_drdy                            (ptx_drdy),              // Templated
     .p_commit                          (1'b0),                  // Templated
     .p_abort                           (1'b0));                  // Templated
 
/* port_ring_tap AUTO_TEMPLATE
 (
    .ro_data                            (ro_data[`PRW_SZ-1:0]),
    .ri_data                            (ri_data[`PRW_SZ-1:0]),
    .prx_\(.*\)    (prx_\1),
    .ptx_\(.*\)    (rttx_\1),
  );
 */
  port_ring_tap #(port_num) ring_tap
    (/*AUTOINST*/
     // Outputs
     .ri_drdy                           (ri_drdy),
     .prx_drdy                          (prx_drdy),              // Templated
     .ro_srdy                           (ro_srdy),
     .ro_data                           (ro_data[`PRW_SZ-1:0]),  // Templated
     .ptx_srdy                          (rttx_srdy),             // Templated
     .ptx_data                          (rttx_data),             // Templated
     .fli_drdy                          (fli_drdy),
     .rarb_req                          (rarb_req),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ri_srdy                           (ri_srdy),
     .ri_data                           (ri_data[`PRW_SZ-1:0]),  // Templated
     .prx_srdy                          (prx_srdy),              // Templated
     .prx_data                          (prx_data),              // Templated
     .ro_drdy                           (ro_drdy),
     .ptx_drdy                          (rttx_drdy),             // Templated
     .fli_srdy                          (fli_srdy),
     .fli_data                          (fli_data[`NUM_PORTS-1:0]),
     .rarb_ack                          (rarb_ack));
 
/* egr_oflow AUTO_TEMPLATE
 (
    .c_\(.*\)    (rttx_\1[]),
    .p_\(.*\)    (ctx_\1[]),
  );
 */
  egr_oflow oflow
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (rttx_drdy),             // Templated
     .p_srdy                            (ctx_srdy),              // Templated
     .p_data                            (ctx_data[`PFW_SZ-1:0]), // Templated
     .p_commit                          (ctx_commit),            // Templated
     .p_abort                           (ctx_abort),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (rttx_srdy),             // Templated
     .c_data                            (rttx_data[`PFW_SZ-1:0]), // Templated
     .tx_usage                          (tx_usage[`TX_USG_SZ-1:0]),
     .p_drdy                            (ctx_drdy));              // Templated
 
/* distributor AUTO_TEMPLATE
 (
    .p_\(.*\)    (txg_\1[]),
 );
 */
  distributor dst
    (/*AUTOINST*/
     // Outputs
     .ptx_drdy                          (ptx_drdy),
     .p_srdy                            (txg_srdy),              // Templated
     .p_code                            (txg_code[1:0]),         // Templated
     .p_data                            (txg_data[7:0]),         // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ptx_srdy                          (ptx_srdy),
     .ptx_data                          (ptx_data[`PFW_SZ-1:0]),
     .p_drdy                            (txg_drdy));              // Templated
 
  sd_tx_gigmac tx_gmii
    (/*AUTOINST*/
     // Outputs
     .gmii_tx_en                        (gmii_tx_en),
     .gmii_txd                          (gmii_txd[7:0]),
     .txg_drdy                          (txg_drdy),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .txg_srdy                          (txg_srdy),
     .txg_code                          (txg_code[1:0]),
     .txg_data                          (txg_data[7:0]));
 
endmodule // port_macro
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	8	ghutchis	`module port_macro`
2	11	ghutchis	`#(parameter port_num = 0)`
3	8	ghutchis	`(input clk,`
4			`input reset,`
5
6			input [`PRW_SZ-1:0] ri_data, // To ring_tap of port_ring_tap.v
7			output [`PRW_SZ-1:0] ro_data, // From ring_tap of port_ring_tap.v
8			input [`NUM_PORTS-1:0] fli_data, // To ring_tap of port_ring_tap.v
9			`/AUTOINPUT/`
10			`// Beginning of automatic inputs (from unused autoinst inputs)`
11	11	ghutchis	`input fli_srdy, // To ring_tap of port_ring_tap.v`
12			`input gmii_rx_clk, // To port_clocking of port_clocking.v, ...`
13			`input gmii_rx_dv, // To rx_gigmac of sd_rx_gigmac.v`
14			`input [7:0] gmii_rxd, // To rx_gigmac of sd_rx_gigmac.v`
15			`input p2f_drdy, // To pkt_parse of pkt_parse.v`
16	12	ghutchis	`input rarb_ack, // To ring_tap of port_ring_tap.v`
17	11	ghutchis	`input ri_srdy, // To ring_tap of port_ring_tap.v`
18			`input ro_drdy, // To ring_tap of port_ring_tap.v`
19	8	ghutchis	`// End of automatics`
20
21	12	ghutchis	`output rarb_req,`
22	8	ghutchis	`output fli_drdy, // From ring_tap of port_ring_tap.v`
23	11	ghutchis	`output gmii_tx_en, // From tx_gmii of sd_tx_gigmac.v`
24	8	ghutchis	`output [7:0] gmii_txd, // From tx_gmii of sd_tx_gigmac.v`
25			output [`PAR_DATA_SZ-1:0] p2f_data, // From pkt_parse of pkt_parse.v
26			`output p2f_srdy, // From pkt_parse of pkt_parse.v`
27			`output ri_drdy, // From ring_tap of port_ring_tap.v`
28			`output ro_srdy // From ring_tap of port_ring_tap.v`
29			`);`
30
31			wire [`RX_USG_SZ-1:0] rx_usage;
32			wire [`TX_USG_SZ-1:0] tx_usage;
33			wire [`PFW_SZ-1:0] prx_data; // From fifo_rx of sd_fifo_b.v
34			wire [`PFW_SZ-1:0] ptx_data; // From fifo_tx of sd_fifo_b.v
35			wire [`PFW_SZ-1:0] rttx_data; // From ring_tap of port_ring_tap.v
36			`wire [1:0] rxg_code; // From rx_sync_fifo of sd_fifo_s.v`
37			`wire [7:0] rxg_data; // From rx_sync_fifo of sd_fifo_s.v`
38			wire [`PFW_SZ-1:0] ctx_data; // From oflow of egr_oflow.v
39			`/AUTOWIRE/`
40			`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
41	11	ghutchis	`wire crx_abort; // From con of concentrator.v`
42			`wire crx_commit; // From con of concentrator.v`
43			wire [`PFW_SZ-1:0] crx_data; // From con of concentrator.v
44			`wire crx_drdy; // From fifo_rx of sd_fifo_b.v`
45			`wire crx_srdy; // From con of concentrator.v`
46			`wire ctx_abort; // From oflow of egr_oflow.v`
47			`wire ctx_commit; // From oflow of egr_oflow.v`
48			`wire ctx_drdy; // From fifo_tx of sd_fifo_b.v`
49			`wire ctx_srdy; // From oflow of egr_oflow.v`
50			`wire gmii_rx_reset; // From port_clocking of port_clocking.v`
51			`wire [1:0] pdo_code; // From pkt_parse of pkt_parse.v`
52			`wire [7:0] pdo_data; // From pkt_parse of pkt_parse.v`
53			`wire pdo_drdy; // From con of concentrator.v`
54			`wire pdo_srdy; // From pkt_parse of pkt_parse.v`
55			`wire prx_drdy; // From ring_tap of port_ring_tap.v`
56			`wire prx_srdy; // From fifo_rx of sd_fifo_b.v`
57			`wire ptx_drdy; // From dst of distributor.v`
58			`wire ptx_srdy; // From fifo_tx of sd_fifo_b.v`
59	12	ghutchis	`wire rarb_req; // From ring_tap of port_ring_tap.v`
60	11	ghutchis	`wire rttx_drdy; // From oflow of egr_oflow.v`
61			`wire rttx_srdy; // From ring_tap of port_ring_tap.v`
62			`wire [1:0] rxc_rxg_code; // From rx_gigmac of sd_rx_gigmac.v`
63			`wire [7:0] rxc_rxg_data; // From rx_gigmac of sd_rx_gigmac.v`
64			`wire rxc_rxg_drdy; // From rx_sync_fifo of sd_fifo_s.v`
65			`wire rxc_rxg_srdy; // From rx_gigmac of sd_rx_gigmac.v`
66			`wire rxg_drdy; // From pkt_parse of pkt_parse.v`
67			`wire rxg_srdy; // From rx_sync_fifo of sd_fifo_s.v`
68			`wire [1:0] txg_code; // From dst of distributor.v`
69			`wire [7:0] txg_data; // From dst of distributor.v`
70			`wire txg_drdy; // From tx_gmii of sd_tx_gigmac.v`
71			`wire txg_srdy; // From dst of distributor.v`
72	8	ghutchis	`// End of automatics`
73
74
75			`port_clocking port_clocking`
76			`(/AUTOINST/`
77			`// Outputs`
78	11	ghutchis	`.gmii_rx_reset (gmii_rx_reset),`
79	8	ghutchis	`// Inputs`
80	11	ghutchis	`.clk (clk),`
81			`.reset (reset),`
82			`.gmii_rx_clk (gmii_rx_clk));`
83	8	ghutchis
84			`/* sd_rx_gigmac AUTO_TEMPLATE`
85			`(`
86			`.clk (gmii_rx_clk),`
87			`.reset (gmii_rx_reset),`
88			`.rxg_\(.*\) (rxc_rxg_\1[]),`
89			`);`
90			`*/`
91			`sd_rx_gigmac rx_gigmac`
92			`(/AUTOINST/`
93			`// Outputs`
94	11	ghutchis	`.rxg_srdy (rxc_rxg_srdy), // Templated`
95			`.rxg_code (rxc_rxg_code[1:0]), // Templated`
96			`.rxg_data (rxc_rxg_data[7:0]), // Templated`
97	8	ghutchis	`// Inputs`
98	11	ghutchis	`.clk (gmii_rx_clk), // Templated`
99			`.reset (gmii_rx_reset), // Templated`
100			`.gmii_rx_dv (gmii_rx_dv),`
101			`.gmii_rxd (gmii_rxd[7:0]),`
102			`.rxg_drdy (rxc_rxg_drdy)); // Templated`
103	8	ghutchis
104			`/* sd_fifo_s AUTO_TEMPLATE`
105			`(`
106			`.c_clk (gmii_rx_clk),`
107			`.c_reset (gmii_rx_reset),`
108			`.c_data ({rxc_rxg_code,rxc_rxg_data}),`
109			`.p_data ({rxg_code,rxg_data}),`
110			`.p_clk (clk),`
111			`.p_reset (reset),`
112			`.c_\(.*\) (rxc_rxg_\1[]),`
113			`.p_\(.*\) (rxg_\1[]),`
114			`);`
115			`*/`
116			`sd_fifo_s #(8+2,16,1) rx_sync_fifo`
117			`(/AUTOINST/`
118			`// Outputs`
119	11	ghutchis	`.c_drdy (rxc_rxg_drdy), // Templated`
120			`.p_srdy (rxg_srdy), // Templated`
121			`.p_data ({rxg_code,rxg_data}), // Templated`
122	8	ghutchis	`// Inputs`
123	11	ghutchis	`.c_clk (gmii_rx_clk), // Templated`
124			`.c_reset (gmii_rx_reset), // Templated`
125			`.c_srdy (rxc_rxg_srdy), // Templated`
126			`.c_data ({rxc_rxg_code,rxc_rxg_data}), // Templated`
127			`.p_clk (clk), // Templated`
128			`.p_reset (reset), // Templated`
129			`.p_drdy (rxg_drdy)); // Templated`
130	8	ghutchis
131	11	ghutchis	`pkt_parse #(port_num) pkt_parse`
132	8	ghutchis	`(/AUTOINST/`
133			`// Outputs`
134	11	ghutchis	`.rxg_drdy (rxg_drdy),`
135			`.p2f_srdy (p2f_srdy),`
136			.p2f_data (p2f_data[`PAR_DATA_SZ-1:0]),
137			`.pdo_srdy (pdo_srdy),`
138			`.pdo_code (pdo_code[1:0]),`
139			`.pdo_data (pdo_data[7:0]),`
140	8	ghutchis	`// Inputs`
141	11	ghutchis	`.clk (clk),`
142			`.reset (reset),`
143			`.rxg_srdy (rxg_srdy),`
144			`.rxg_code (rxg_code[1:0]),`
145			`.rxg_data (rxg_data[7:0]),`
146			`.p2f_drdy (p2f_drdy),`
147			`.pdo_drdy (pdo_drdy));`
148	8	ghutchis
149			`/* concentrator AUTO_TEMPLATE`
150			`(`
151			`.c_\(.*\) (pdo_\1[]),`
152			`.p_\(.*\) (crx_\1[]),`
153			`);`
154			`*/`
155			`concentrator con`
156			`(/AUTOINST/`
157			`// Outputs`
158	11	ghutchis	`.c_drdy (pdo_drdy), // Templated`
159			.p_data (crx_data[`PFW_SZ-1:0]), // Templated
160			`.p_srdy (crx_srdy), // Templated`
161			`.p_commit (crx_commit), // Templated`
162			`.p_abort (crx_abort), // Templated`
163	8	ghutchis	`// Inputs`
164	11	ghutchis	`.clk (clk),`
165			`.reset (reset),`
166			`.c_data (pdo_data[7:0]), // Templated`
167			`.c_code (pdo_code[1:0]), // Templated`
168			`.c_srdy (pdo_srdy), // Templated`
169			`.p_drdy (crx_drdy)); // Templated`
170	8	ghutchis
171			`/* sd_fifo_b AUTO_TEMPLATE "fifo_\(.*\)"`
172			`(`
173			`.p_abort (1'b0),`
174			`.p_commit (1'b0),`
175			`.usage (@_usage),`
176			`.c_\(.*\) (c@_\1),`
177			`.p_\(.*\) (p@_\1),`
178			`);`
179			`*/`
180			sd_fifo_b #(`PFW_SZ, `RX_FIFO_DEPTH, 0, 1) fifo_rx
181			`(/AUTOINST/`
182			`// Outputs`
183	11	ghutchis	`.c_drdy (crx_drdy), // Templated`
184			`.p_srdy (prx_srdy), // Templated`
185			`.p_data (prx_data), // Templated`
186			`.usage (rx_usage), // Templated`
187	8	ghutchis	`// Inputs`
188	11	ghutchis	`.clk (clk),`
189			`.reset (reset),`
190			`.c_srdy (crx_srdy), // Templated`
191			`.c_commit (crx_commit), // Templated`
192			`.c_abort (crx_abort), // Templated`
193			`.c_data (crx_data), // Templated`
194			`.p_drdy (prx_drdy), // Templated`
195			`.p_commit (1'b0), // Templated`
196			`.p_abort (1'b0)); // Templated`
197	8	ghutchis
198			sd_fifo_b #(`PFW_SZ, `TX_FIFO_DEPTH, 0, 1) fifo_tx
199			`(/AUTOINST/`
200			`// Outputs`
201	11	ghutchis	`.c_drdy (ctx_drdy), // Templated`
202			`.p_srdy (ptx_srdy), // Templated`
203			`.p_data (ptx_data), // Templated`
204			`.usage (tx_usage), // Templated`
205	8	ghutchis	`// Inputs`
206	11	ghutchis	`.clk (clk),`
207			`.reset (reset),`
208			`.c_srdy (ctx_srdy), // Templated`
209			`.c_commit (ctx_commit), // Templated`
210			`.c_abort (ctx_abort), // Templated`
211			`.c_data (ctx_data), // Templated`
212			`.p_drdy (ptx_drdy), // Templated`
213			`.p_commit (1'b0), // Templated`
214			`.p_abort (1'b0)); // Templated`
215	8	ghutchis
216			`/* port_ring_tap AUTO_TEMPLATE`
217			`(`
218			.ro_data (ro_data[`PRW_SZ-1:0]),
219			.ri_data (ri_data[`PRW_SZ-1:0]),
220			`.prx_\(.*\) (prx_\1),`
221			`.ptx_\(.*\) (rttx_\1),`
222			`);`
223			`*/`
224	11	ghutchis	`port_ring_tap #(port_num) ring_tap`
225	8	ghutchis	`(/AUTOINST/`
226			`// Outputs`
227	11	ghutchis	`.ri_drdy (ri_drdy),`
228			`.prx_drdy (prx_drdy), // Templated`
229			`.ro_srdy (ro_srdy),`
230			.ro_data (ro_data[`PRW_SZ-1:0]), // Templated
231			`.ptx_srdy (rttx_srdy), // Templated`
232			`.ptx_data (rttx_data), // Templated`
233			`.fli_drdy (fli_drdy),`
234	12	ghutchis	`.rarb_req (rarb_req),`
235	8	ghutchis	`// Inputs`
236	11	ghutchis	`.clk (clk),`
237			`.reset (reset),`
238			`.ri_srdy (ri_srdy),`
239			.ri_data (ri_data[`PRW_SZ-1:0]), // Templated
240			`.prx_srdy (prx_srdy), // Templated`
241			`.prx_data (prx_data), // Templated`
242			`.ro_drdy (ro_drdy),`
243			`.ptx_drdy (rttx_drdy), // Templated`
244			`.fli_srdy (fli_srdy),`
245	12	ghutchis	.fli_data (fli_data[`NUM_PORTS-1:0]),
246			`.rarb_ack (rarb_ack));`
247	8	ghutchis
248			`/* egr_oflow AUTO_TEMPLATE`
249			`(`
250			`.c_\(.*\) (rttx_\1[]),`
251			`.p_\(.*\) (ctx_\1[]),`
252			`);`
253			`*/`
254			`egr_oflow oflow`
255			`(/AUTOINST/`
256			`// Outputs`
257	11	ghutchis	`.c_drdy (rttx_drdy), // Templated`
258			`.p_srdy (ctx_srdy), // Templated`
259			.p_data (ctx_data[`PFW_SZ-1:0]), // Templated
260			`.p_commit (ctx_commit), // Templated`
261			`.p_abort (ctx_abort), // Templated`
262	8	ghutchis	`// Inputs`
263	11	ghutchis	`.clk (clk),`
264			`.reset (reset),`
265			`.c_srdy (rttx_srdy), // Templated`
266			.c_data (rttx_data[`PFW_SZ-1:0]), // Templated
267			.tx_usage (tx_usage[`TX_USG_SZ-1:0]),
268			`.p_drdy (ctx_drdy)); // Templated`
269	8	ghutchis
270			`/* distributor AUTO_TEMPLATE`
271			`(`
272			`.p_\(.*\) (txg_\1[]),`
273			`);`
274			`*/`
275			`distributor dst`
276			`(/AUTOINST/`
277			`// Outputs`
278	11	ghutchis	`.ptx_drdy (ptx_drdy),`
279			`.p_srdy (txg_srdy), // Templated`
280			`.p_code (txg_code[1:0]), // Templated`
281			`.p_data (txg_data[7:0]), // Templated`
282	8	ghutchis	`// Inputs`
283	11	ghutchis	`.clk (clk),`
284			`.reset (reset),`
285			`.ptx_srdy (ptx_srdy),`
286			.ptx_data (ptx_data[`PFW_SZ-1:0]),
287			`.p_drdy (txg_drdy)); // Templated`
288	8	ghutchis
289			`sd_tx_gigmac tx_gmii`
290			`(/AUTOINST/`
291			`// Outputs`
292	11	ghutchis	`.gmii_tx_en (gmii_tx_en),`
293			`.gmii_txd (gmii_txd[7:0]),`
294			`.txg_drdy (txg_drdy),`
295	8	ghutchis	`// Inputs`
296	11	ghutchis	`.clk (clk),`
297			`.reset (reset),`
298			`.txg_srdy (txg_srdy),`
299			`.txg_code (txg_code[1:0]),`
300			`.txg_data (txg_data[7:0]));`
301	8	ghutchis
302			`endmodule // port_macro`
303			`// Local Variables:`
304			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/buffers" "../../../rtl/verilog/forks")`
305			`// End:`

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