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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap.v] - Blame information for rev 12

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// Inputs are ri (Ring In), ro (Ring Out),
// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)
 
module port_ring_tap
  #(parameter portnum = 0,
    parameter rdp_sz = `PRW_SZ,
    parameter pdp_sz = `PFW_SZ
    )
  (
   input         clk,
   input         reset,
 
   input         ri_srdy,
   output        ri_drdy,
   input [rdp_sz-1:0] ri_data,
 
   input         prx_srdy,
   output        prx_drdy,
   input [pdp_sz-1:0] prx_data,
 
   output        ro_srdy,
   input         ro_drdy,
   output [rdp_sz-1:0] ro_data,
 
   output        ptx_srdy,
   input         ptx_drdy,
   output [pdp_sz-1:0] ptx_data,
 
   input         fli_srdy,
   output        fli_drdy,
   input [`NUM_PORTS-1:0] fli_data,
 
   output        rarb_req,
   input         rarb_ack
   );
 
  wire [`PRW_SZ-1:0]     lri_data;               // From tc_ri of sd_input.v
  wire [`NUM_PORTS-1:0]  lfli_data;              // From tc_fli of sd_input.v
  wire [`PFW_SZ-1:0]     lprx_data;              // From tc_prx of sd_input.v
  wire [`PFW_SZ-1:0]     lptx_data;              // From fsm of port_ring_tap_fsm.v
  wire [`PRW_SZ-1:0]     lro_data;               // From fsm of port_ring_tap_fsm.v
  /*AUTOWIRE*/
  // Beginning of automatic wires (for undeclared instantiated-module outputs)
  wire                  lfli_drdy;              // From fsm of port_ring_tap_fsm.v
  wire                  lfli_srdy;              // From tc_fli of sd_input.v
  wire                  lprx_drdy;              // From fsm of port_ring_tap_fsm.v
  wire                  lprx_srdy;              // From tc_prx of sd_input.v
  wire                  lptx_drdy;              // From tc_ptx of sd_output.v
  wire                  lptx_srdy;              // From fsm of port_ring_tap_fsm.v
  wire                  lri_drdy;               // From fsm of port_ring_tap_fsm.v
  wire                  lri_srdy;               // From tc_ri of sd_input.v
  wire                  lro_drdy;               // From tc_ro of sd_output.v
  wire                  lro_srdy;               // From fsm of port_ring_tap_fsm.v
  // End of automatics
 
  /* sd_input AUTO_TEMPLATE "tc_\(.*\)"
   (
    .c_\(.*\)     (@_\1),
    .ip_\(.*\)    (l@_\1),
   );
   */
 
  sd_input #(rdp_sz) tc_ri
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (ri_drdy),               // Templated
     .ip_srdy                           (lri_srdy),              // Templated
     .ip_data                           (lri_data),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (ri_srdy),               // Templated
     .c_data                            (ri_data),               // Templated
     .ip_drdy                           (lri_drdy));              // Templated
 
  sd_input #(pdp_sz) tc_prx
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (prx_drdy),              // Templated
     .ip_srdy                           (lprx_srdy),             // Templated
     .ip_data                           (lprx_data),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (prx_srdy),              // Templated
     .c_data                            (prx_data),              // Templated
     .ip_drdy                           (lprx_drdy));             // Templated
 
  sd_input #(`NUM_PORTS) tc_fli
    (/*AUTOINST*/
     // Outputs
     .c_drdy                            (fli_drdy),              // Templated
     .ip_srdy                           (lfli_srdy),             // Templated
     .ip_data                           (lfli_data),             // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .c_srdy                            (fli_srdy),              // Templated
     .c_data                            (fli_data),              // Templated
     .ip_drdy                           (lfli_drdy));             // Templated
 
  port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm
    (/*AUTOINST*/
     // Outputs
     .lfli_drdy                         (lfli_drdy),
     .lprx_drdy                         (lprx_drdy),
     .lptx_data                         (lptx_data[pdp_sz-1:0]),
     .lptx_srdy                         (lptx_srdy),
     .lri_drdy                          (lri_drdy),
     .lro_data                          (lro_data[rdp_sz-1:0]),
     .lro_srdy                          (lro_srdy),
     .rarb_req                          (rarb_req),
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .lfli_data                         (lfli_data[`NUM_PORTS-1:0]),
     .lfli_srdy                         (lfli_srdy),
     .lprx_data                         (lprx_data[pdp_sz-1:0]),
     .lprx_srdy                         (lprx_srdy),
     .lptx_drdy                         (lptx_drdy),
     .lri_data                          (lri_data[rdp_sz-1:0]),
     .lri_srdy                          (lri_srdy),
     .lro_drdy                          (lro_drdy),
     .rarb_ack                          (rarb_ack));
 
  /* sd_output AUTO_TEMPLATE "tc_\(.*\)"
   (
    .ic_\(.*\)    (l@_\1),
    .p_\(.*\)     (@_\1),
   );
   */
 
  sd_output #(pdp_sz) tc_ptx
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (lptx_drdy),             // Templated
     .p_srdy                            (ptx_srdy),              // Templated
     .p_data                            (ptx_data),              // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (lptx_srdy),             // Templated
     .ic_data                           (lptx_data),             // Templated
     .p_drdy                            (ptx_drdy));              // Templated
 
  sd_output #(rdp_sz) tc_ro
    (/*AUTOINST*/
     // Outputs
     .ic_drdy                           (lro_drdy),              // Templated
     .p_srdy                            (ro_srdy),               // Templated
     .p_data                            (ro_data),               // Templated
     // Inputs
     .clk                               (clk),
     .reset                             (reset),
     .ic_srdy                           (lro_srdy),              // Templated
     .ic_data                           (lro_data),              // Templated
     .p_drdy                            (ro_drdy));               // Templated
 
endmodule // port_ring_tap
// Local Variables:
// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")
// End:  

Line No.	Rev	Author	Line
1	5	ghutchis	`// Inputs are ri (Ring In), ro (Ring Out),`
2			`// fli (FIB lookup in), prx (port in/RX), and ptx (port out/TX)`
3
4			`module port_ring_tap`
5	11	ghutchis	`#(parameter portnum = 0,`
6			parameter rdp_sz = `PRW_SZ,
7			parameter pdp_sz = `PFW_SZ
8			`)`
9	5	ghutchis	`(`
10			`input clk,`
11			`input reset,`
12
13			`input ri_srdy,`
14			`output ri_drdy,`
15			`input [rdp_sz-1:0] ri_data,`
16
17			`input prx_srdy,`
18			`output prx_drdy,`
19	8	ghutchis	`input [pdp_sz-1:0] prx_data,`
20	5	ghutchis
21			`output ro_srdy,`
22			`input ro_drdy,`
23			`output [rdp_sz-1:0] ro_data,`
24
25			`output ptx_srdy,`
26			`input ptx_drdy,`
27	8	ghutchis	`output [pdp_sz-1:0] ptx_data,`
28	5	ghutchis
29			`input fli_srdy,`
30			`output fli_drdy,`
31	12	ghutchis	input [`NUM_PORTS-1:0] fli_data,
32
33			`output rarb_req,`
34			`input rarb_ack`
35	5	ghutchis	`);`
36
37	8	ghutchis	wire [`PRW_SZ-1:0] lri_data; // From tc_ri of sd_input.v
38			wire [`NUM_PORTS-1:0] lfli_data; // From tc_fli of sd_input.v
39			wire [`PFW_SZ-1:0] lprx_data; // From tc_prx of sd_input.v
40			wire [`PFW_SZ-1:0] lptx_data; // From fsm of port_ring_tap_fsm.v
41			wire [`PRW_SZ-1:0] lro_data; // From fsm of port_ring_tap_fsm.v
42	5	ghutchis	`/AUTOWIRE/`
43	8	ghutchis	`// Beginning of automatic wires (for undeclared instantiated-module outputs)`
44	12	ghutchis	`wire lfli_drdy; // From fsm of port_ring_tap_fsm.v`
45			`wire lfli_srdy; // From tc_fli of sd_input.v`
46			`wire lprx_drdy; // From fsm of port_ring_tap_fsm.v`
47			`wire lprx_srdy; // From tc_prx of sd_input.v`
48			`wire lptx_drdy; // From tc_ptx of sd_output.v`
49			`wire lptx_srdy; // From fsm of port_ring_tap_fsm.v`
50			`wire lri_drdy; // From fsm of port_ring_tap_fsm.v`
51			`wire lri_srdy; // From tc_ri of sd_input.v`
52			`wire lro_drdy; // From tc_ro of sd_output.v`
53			`wire lro_srdy; // From fsm of port_ring_tap_fsm.v`
54	8	ghutchis	`// End of automatics`
55	5	ghutchis
56			`/* sd_input AUTO_TEMPLATE "tc_\(.*\)"`
57			`(`
58	8	ghutchis	`.c_\(.*\) (@_\1),`
59			`.ip_\(.*\) (l@_\1),`
60	5	ghutchis	`);`
61			`*/`
62
63			`sd_input #(rdp_sz) tc_ri`
64			`(/AUTOINST/`
65			`// Outputs`
66	12	ghutchis	`.c_drdy (ri_drdy), // Templated`
67			`.ip_srdy (lri_srdy), // Templated`
68			`.ip_data (lri_data), // Templated`
69	5	ghutchis	`// Inputs`
70	12	ghutchis	`.clk (clk),`
71			`.reset (reset),`
72			`.c_srdy (ri_srdy), // Templated`
73			`.c_data (ri_data), // Templated`
74			`.ip_drdy (lri_drdy)); // Templated`
75	5	ghutchis
76	8	ghutchis	`sd_input #(pdp_sz) tc_prx`
77	5	ghutchis	`(/AUTOINST/`
78			`// Outputs`
79	12	ghutchis	`.c_drdy (prx_drdy), // Templated`
80			`.ip_srdy (lprx_srdy), // Templated`
81			`.ip_data (lprx_data), // Templated`
82	5	ghutchis	`// Inputs`
83	12	ghutchis	`.clk (clk),`
84			`.reset (reset),`
85			`.c_srdy (prx_srdy), // Templated`
86			`.c_data (prx_data), // Templated`
87			`.ip_drdy (lprx_drdy)); // Templated`
88	5	ghutchis
89			sd_input #(`NUM_PORTS) tc_fli
90			`(/AUTOINST/`
91			`// Outputs`
92	12	ghutchis	`.c_drdy (fli_drdy), // Templated`
93			`.ip_srdy (lfli_srdy), // Templated`
94			`.ip_data (lfli_data), // Templated`
95	5	ghutchis	`// Inputs`
96	12	ghutchis	`.clk (clk),`
97			`.reset (reset),`
98			`.c_srdy (fli_srdy), // Templated`
99			`.c_data (fli_data), // Templated`
100			`.ip_drdy (lfli_drdy)); // Templated`
101	5	ghutchis
102	8	ghutchis	`port_ring_tap_fsm #(rdp_sz, pdp_sz, portnum) fsm`
103			`(/AUTOINST/`
104			`// Outputs`
105	12	ghutchis	`.lfli_drdy (lfli_drdy),`
106			`.lprx_drdy (lprx_drdy),`
107			`.lptx_data (lptx_data[pdp_sz-1:0]),`
108			`.lptx_srdy (lptx_srdy),`
109			`.lri_drdy (lri_drdy),`
110			`.lro_data (lro_data[rdp_sz-1:0]),`
111			`.lro_srdy (lro_srdy),`
112			`.rarb_req (rarb_req),`
113	8	ghutchis	`// Inputs`
114	12	ghutchis	`.clk (clk),`
115			`.reset (reset),`
116			.lfli_data (lfli_data[`NUM_PORTS-1:0]),
117			`.lfli_srdy (lfli_srdy),`
118			`.lprx_data (lprx_data[pdp_sz-1:0]),`
119			`.lprx_srdy (lprx_srdy),`
120			`.lptx_drdy (lptx_drdy),`
121			`.lri_data (lri_data[rdp_sz-1:0]),`
122			`.lri_srdy (lri_srdy),`
123			`.lro_drdy (lro_drdy),`
124			`.rarb_ack (rarb_ack));`
125	8	ghutchis
126	5	ghutchis	`/* sd_output AUTO_TEMPLATE "tc_\(.*\)"`
127			`(`
128	8	ghutchis	`.ic_\(.*\) (l@_\1),`
129			`.p_\(.*\) (@_\1),`
130	5	ghutchis	`);`
131			`*/`
132
133	8	ghutchis	`sd_output #(pdp_sz) tc_ptx`
134	5	ghutchis	`(/AUTOINST/`
135			`// Outputs`
136	12	ghutchis	`.ic_drdy (lptx_drdy), // Templated`
137			`.p_srdy (ptx_srdy), // Templated`
138			`.p_data (ptx_data), // Templated`
139	5	ghutchis	`// Inputs`
140	12	ghutchis	`.clk (clk),`
141			`.reset (reset),`
142			`.ic_srdy (lptx_srdy), // Templated`
143			`.ic_data (lptx_data), // Templated`
144			`.p_drdy (ptx_drdy)); // Templated`
145	5	ghutchis
146			`sd_output #(rdp_sz) tc_ro`
147			`(/AUTOINST/`
148			`// Outputs`
149	12	ghutchis	`.ic_drdy (lro_drdy), // Templated`
150			`.p_srdy (ro_srdy), // Templated`
151			`.p_data (ro_data), // Templated`
152	5	ghutchis	`// Inputs`
153	12	ghutchis	`.clk (clk),`
154			`.reset (reset),`
155			`.ic_srdy (lro_srdy), // Templated`
156			`.ic_data (lro_data), // Templated`
157			`.p_drdy (ro_drdy)); // Templated`
158	5	ghutchis
159			`endmodule // port_ring_tap`
160			`// Local Variables:`
161			`// verilog-library-directories:("." "../../../rtl/verilog/closure" "../../../rtl/verilog/memory" "../../../rtl/verilog/forks")`
162			`// End:`

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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [port_ring_tap.v] - Blame information for rev 12