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[/] [srdydrdy_lib/] [trunk/] [examples/] [bridge/] [rtl/] [ring_arb.v] - Blame information for rev 12

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1 12 ghutchis
module ring_arb
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  (
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   input        clk,
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   input        reset,
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   input [`NUM_PORTS-1:0] rarb_req,
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   output reg [`NUM_PORTS-1:0] rarb_ack
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   );
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  integer                      i;
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  reg [`NUM_PORTS-1:0]         nxt_rarb_ack;
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  reg [$clog2(`NUM_PORTS)-1:0] nxt_ack;
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  always @*
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    begin
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      nxt_rarb_ack = rarb_ack;
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      nxt_ack = 0;
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      if (rarb_req == 0)
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        nxt_rarb_ack = 0;
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      else if ((rarb_ack == 0) |
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          ((rarb_req & rarb_ack) == 0))
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        begin
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          nxt_ack = 0;
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          for (i=`NUM_PORTS; i>0; i=i-1)
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            if (rarb_req[i-1])
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              nxt_ack = i-1;
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          nxt_rarb_ack = 1 << nxt_ack;
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        end
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    end // always @ *
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  always @(posedge clk)
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    begin
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      if (reset)
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        rarb_ack <= #1 0;
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      else
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        rarb_ack <= #1 nxt_rarb_ack;
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    end
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endmodule // ring_arb

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