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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_FF.v                                                 ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: MAC_rx_FF.v,v $
// Revision 1.5  2006/06/25 04:58:56  maverickist
// no message
//
// Revision 1.4  2006/05/28 05:09:20  maverickist
// no message
//
// Revision 1.3  2006/01/19 14:07:54  maverickist
// verification is complete.
//
// Revision 1.3  2005/12/16 06:44:16  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:37  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_rx_FF (
Reset       ,
Clk_MAC     ,
Clk_SYS     ,
//MAC_rx_ctrl interface                                                                                                                                          
Fifo_data       ,
Fifo_data_en    ,
Fifo_full       ,
Fifo_data_err   ,
Fifo_data_end   ,
//CPU
Rx_Hwmark,
Rx_Lwmark,
RX_APPEND_CRC,
//user interface                                                                                                                                               
Rx_mac_ra   ,
Rx_mac_rd   ,
Rx_mac_data ,
Rx_mac_BE   ,
Rx_mac_sop  ,
Rx_mac_pa,
Rx_mac_eop
);
input           Reset       ;
input           Clk_MAC     ;
input           Clk_SYS     ;
                //MAC_rx_ctrl interface 
input   [7:0]   Fifo_data       ;
input           Fifo_data_en    ;
output          Fifo_full       ;
input           Fifo_data_err   ;
input           Fifo_data_end   ;
                //CPU
input           RX_APPEND_CRC       ;
input   [4:0]   Rx_Hwmark           ;
input   [4:0]   Rx_Lwmark           ;
                //user interface 
output          Rx_mac_ra   ;//
input           Rx_mac_rd   ;
output  [31:0]  Rx_mac_data ;
output  [1:0]   Rx_mac_BE   ;
output          Rx_mac_pa   ;
output          Rx_mac_sop  ;
output          Rx_mac_eop  ;
 
//******************************************************************************
//internal signals                                                              
//******************************************************************************
parameter       State_byte3     =4'd0;
parameter       State_byte2     =4'd1;
parameter       State_byte1     =4'd2;
parameter       State_byte0     =4'd3;
parameter       State_be0       =4'd4;
parameter       State_be3       =4'd5;
parameter       State_be2       =4'd6;
parameter       State_be1       =4'd7;
parameter       State_err_end   =4'd8;
parameter       State_idle      =4'd9;
 
parameter       SYS_read        =3'd0;
parameter       SYS_pause       =3'd1;
parameter       SYS_wait_end    =3'd2;
parameter       SYS_idle        =3'd3;
parameter       FF_emtpy_err    =3'd4;
 
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_ungray;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_gray;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_gray_dl1;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_wr_reg;
 
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd_gray;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd_gray_dl1;
reg [`MAC_TX_FF_DEPTH-1:0]       Add_rd_ungray;
reg [35:0]      Din;
reg [35:0]      Din_tmp;
reg [35:0]      Din_tmp_reg;
wire[35:0]      Dout;
reg             Wr_en;
reg             Wr_en_tmp;
reg             Wr_en_ptr;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse4;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse3;
wire[`MAC_TX_FF_DEPTH-1:0]       Add_wr_pluse2;
reg             Full;
reg             Almost_full;
reg             Empty /* synthesis syn_keep=1 */;
reg [3:0]       Current_state /* synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [7:0]       Fifo_data_byte0;
reg [7:0]       Fifo_data_byte1;
reg [7:0]       Fifo_data_byte2;
reg [7:0]       Fifo_data_byte3;
reg             Fifo_data_en_dl1;
reg [7:0]       Fifo_data_dl1;
reg             Rx_mac_sop_tmp  ;
reg             Rx_mac_sop  ;
reg             Rx_mac_ra   ;
reg             Rx_mac_pa   ;
 
 
 
reg [2:0]       Current_state_SYS /* synthesis syn_keep=1 */;
reg [2:0]       Next_state_SYS ;
reg [5:0]       Packet_number_inFF /* synthesis syn_keep=1 */;
reg             Packet_number_sub ;
wire            Packet_number_add_edge;
reg             Packet_number_add_dl1;
reg             Packet_number_add_dl2;
reg             Packet_number_add ;
reg             Packet_number_add_tmp    ;
reg             Packet_number_add_tmp_dl1;
reg             Packet_number_add_tmp_dl2;
 
reg             Rx_mac_sop_tmp_dl1;
reg [35:0]      Dout_dl1;
reg [4:0]       Fifo_data_count;
reg             Rx_mac_pa_tmp       ;
reg             Add_wr_jump_tmp     ;
reg             Add_wr_jump_tmp_pl1 ;
reg             Add_wr_jump         ;
reg             Add_wr_jump_rd_pl1  ;
reg [4:0]       Rx_Hwmark_pl        ;
reg [4:0]       Rx_Lwmark_pl        ;
integer         i                   ;
//******************************************************************************
//domain Clk_MAC,write data to dprom.a-port for write
//******************************************************************************    
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Current_state   <=State_idle;
    else
        Current_state   <=Next_state;
 
always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)
    case (Current_state)
        State_idle:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else
                    Next_state  =Current_state;
        State_byte3:
                if (Fifo_data_en)
                    Next_state  =State_byte2;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be1;
                else
                    Next_state  =Current_state;
        State_byte2:
                if (Fifo_data_en)
                    Next_state  =State_byte1;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be2;
                else
                    Next_state  =Current_state;
        State_byte1:
                if (Fifo_data_en)
                    Next_state  =State_byte0;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be3;
                else
                    Next_state  =Current_state;
        State_byte0:
                if (Fifo_data_en)
                    Next_state  =State_byte3;
                else if (Fifo_data_err)
                    Next_state  =State_err_end;
                else if (Fifo_data_end)
                    Next_state  =State_be0;
                else
                    Next_state  =Current_state;
        State_be1:
                Next_state      =State_idle;
        State_be2:
                Next_state      =State_idle;
        State_be3:
                Next_state      =State_idle;
        State_be0:
                Next_state      =State_idle;
        State_err_end:
                Next_state      =State_idle;
        default:
                Next_state      =State_idle;
    endcase
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr_reg      <=0;
    else if (Current_state==State_idle)
        Add_wr_reg      <=Add_wr;
 
//
 
 
always @ (posedge Reset or posedge Clk_MAC)
    if (Reset)
        Add_wr_gray         <=0;
    else
                begin
                Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_wr_gray[i]                  <=Add_wr[i+1]^Add_wr[i];
                end
 
//
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_gray_dl1         <=0;
    else
        Add_rd_gray_dl1         <=Add_rd_gray;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_rd_ungray       =0;
    else
                begin
                Add_rd_ungray[`MAC_RX_FF_DEPTH-1]       =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        Add_rd_ungray[i]        =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
                end
assign          Add_wr_pluse=Add_wr+1;
assign          Add_wr_pluse4=Add_wr+4;
assign          Add_wr_pluse3=Add_wr+3;
assign          Add_wr_pluse2=Add_wr+2;
 
 
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Full    <=0;
    else if (Add_wr_pluse==Add_rd_ungray)
        Full    <=1;
    else
        Full    <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
                Almost_full     <=0;
        else if (Add_wr_pluse4==Add_rd_ungray||
                 Add_wr_pluse3==Add_rd_ungray||
                 Add_wr_pluse2==Add_rd_ungray||
                 Add_wr_pluse==Add_rd_ungray
                 )
                Almost_full     <=1;
        else
                Almost_full     <=0;
 
assign          Fifo_full =Almost_full;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Add_wr  <=0;
    else if (Current_state==State_err_end)
        Add_wr  <=Add_wr_reg;
    else if (Wr_en&&!Full)
        Add_wr  <=Add_wr +1;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump_tmp <=1;
        else
            Add_wr_jump_tmp <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump_tmp_pl1 <=0;
        else
            Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
        if (Reset)
            Add_wr_jump <=0;
        else if (Current_state==State_err_end)
            Add_wr_jump <=1;
        else if (Add_wr_jump_tmp_pl1)
            Add_wr_jump <=0;
 
//
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_en_dl1    <=0;
    else
        Fifo_data_en_dl1    <=Fifo_data_en;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_dl1   <=0;
    else
        Fifo_data_dl1   <=Fifo_data;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte3     <=0;
    else if (Current_state==State_byte3&&Fifo_data_en_dl1)
        Fifo_data_byte3     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte2     <=0;
    else if (Current_state==State_byte2&&Fifo_data_en_dl1)
        Fifo_data_byte2     <=Fifo_data_dl1;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Fifo_data_byte1     <=0;
    else if (Current_state==State_byte1&&Fifo_data_en_dl1)
        Fifo_data_byte1     <=Fifo_data_dl1;
 
always @ (* )
    case (Current_state)
        State_be0:
            Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
        State_be1:
            Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};
        State_be2:
            Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
        State_be3:
            Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
        default:
            Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
    endcase
 
always @ (*)
    if (Current_state==State_be0||Current_state==State_be1||
       Current_state==State_be2||Current_state==State_be3||
      (Current_state==State_byte0&&Fifo_data_en))
        Wr_en_tmp   =1;
    else
        Wr_en_tmp   =0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Din_tmp_reg <=0;
    else if(Wr_en_tmp)
        Din_tmp_reg <=Din_tmp;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Wr_en_ptr   <=0;
    else if(Current_state==State_idle)
        Wr_en_ptr   <=0;
    else if(Wr_en_tmp)
        Wr_en_ptr   <=1;
 
//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Wr_en           <=0;
        Din             <=0;
        end
    else if(RX_APPEND_CRC)
        begin
        Wr_en           <=Wr_en_tmp;
        Din             <=Din_tmp;
        end
    else
        begin
        Wr_en           <=Wr_en_tmp&&Wr_en_ptr;
        Din             <={Din_tmp[35:32],Din_tmp_reg[31:0]};
        end
 
//this signal for read side to handle the packet number in fifo
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add_tmp   <=0;
    else if (Current_state==State_be0||Current_state==State_be1||
             Current_state==State_be2||Current_state==State_be3)
        Packet_number_add_tmp   <=1;
    else
        Packet_number_add_tmp   <=0;
 
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_tmp_dl1   <=0;
        Packet_number_add_tmp_dl2   <=0;
        end
    else
        begin
        Packet_number_add_tmp_dl1   <=Packet_number_add_tmp;
        Packet_number_add_tmp_dl2   <=Packet_number_add_tmp_dl1;
        end
 
//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.       
//expand to two cycles long almost=16 ns
//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles       
always @ (posedge Clk_MAC or posedge Reset)
    if (Reset)
        Packet_number_add   <=0;
    else if (Packet_number_add_tmp_dl1||Packet_number_add_tmp_dl2)
        Packet_number_add   <=1;
    else
        Packet_number_add   <=0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//******************************************************************************
//domain Clk_SYS,read data from dprom.b-port for read
//******************************************************************************
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Current_state_SYS   <=SYS_idle;
    else
        Current_state_SYS   <=Next_state_SYS;
 
always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)
    case (Current_state_SYS)
        SYS_idle:
                        if (Rx_mac_rd&&Rx_mac_ra&&!Empty)
                Next_state_SYS  =SYS_read;
                    else if(Rx_mac_rd&&Rx_mac_ra&&Empty)
                        Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_read:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_pause;
            else if (Dout[35])
                Next_state_SYS  =SYS_wait_end;
            else if (Empty)
                Next_state_SYS  =FF_emtpy_err;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_pause:
            if (Rx_mac_rd)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        FF_emtpy_err:
            if (!Empty)
                Next_state_SYS  =SYS_read;
            else
                Next_state_SYS  =Current_state_SYS;
        SYS_wait_end:
            if (!Rx_mac_rd)
                Next_state_SYS  =SYS_idle;
            else
                Next_state_SYS  =Current_state_SYS;
        default:
                Next_state_SYS  =SYS_idle;
    endcase
 
 
//gen Rx_mac_ra 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Packet_number_add_dl1   <=0;
        Packet_number_add_dl2   <=0;
        end
    else
        begin
        Packet_number_add_dl1   <=Packet_number_add;
        Packet_number_add_dl2   <=Packet_number_add_dl1;
        end
assign  Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;
 
always @ (Current_state_SYS or Next_state_SYS)
    if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)
        Packet_number_sub       =1;
    else
        Packet_number_sub       =0;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Packet_number_inFF      <=0;
    else if (Packet_number_add_edge&&!Packet_number_sub)
        Packet_number_inFF      <=Packet_number_inFF + 1;
        else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)
        Packet_number_inFF      <=Packet_number_inFF - 1;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Fifo_data_count     <=0;
    else
        Fifo_data_count     <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_Hwmark_pl        <=0;
        Rx_Lwmark_pl        <=0;
        end
    else
        begin
        Rx_Hwmark_pl        <=Rx_Hwmark;
        Rx_Lwmark_pl        <=Rx_Lwmark;
        end
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)
        Rx_mac_ra   <=0;
    else if (Packet_number_inFF>=1||Fifo_data_count>=Rx_Hwmark_pl)
        Rx_mac_ra   <=1;
 
 
//control Add_rd signal;
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_rd      <=0;
    else if (Current_state_SYS==SYS_read&&!Dout[35])
        Add_rd      <=Add_rd + 1;
 
//
always @ (posedge Reset or posedge Clk_SYS)
    if (Reset)
        Add_rd_gray         <=0;
    else
                begin
                Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                Add_rd_gray[i]                  <=Add_rd[i+1]^Add_rd[i];
                end
//
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_gray_dl1     <=0;
    else
        Add_wr_gray_dl1     <=Add_wr_gray;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_jump_rd_pl1  <=0;
    else
        Add_wr_jump_rd_pl1  <=Add_wr_jump;
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Add_wr_ungray       =0;
    else if (!Add_wr_jump_rd_pl1)
                begin
                Add_wr_ungray[`MAC_RX_FF_DEPTH-1]       =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
                for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
                        Add_wr_ungray[i]        =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
                end
//empty signal gen  
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Empty   <=1;
    else if (Add_rd==Add_wr_ungray)
        Empty   <=1;
    else
        Empty   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Dout_dl1    <=0;
    else
        Dout_dl1    <=Dout;
 
assign  Rx_mac_data     =Dout_dl1[31:0];
assign  Rx_mac_BE       =Dout_dl1[33:32];
assign  Rx_mac_eop      =Dout_dl1[35];
 
//aligned to Addr_rd 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa_tmp   <=0;
    else if (Current_state_SYS==SYS_read&&!Dout[35])
        Rx_mac_pa_tmp   <=1;
    else
        Rx_mac_pa_tmp   <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_pa   <=0;
    else
        Rx_mac_pa   <=Rx_mac_pa_tmp;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        Rx_mac_sop_tmp      <=0;
    else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)
        Rx_mac_sop_tmp      <=1;
    else
        Rx_mac_sop_tmp      <=0;
 
 
 
always @ (posedge Clk_SYS or posedge Reset)
    if (Reset)
        begin
        Rx_mac_sop_tmp_dl1  <=0;
        Rx_mac_sop          <=0;
        end
    else
        begin
        Rx_mac_sop_tmp_dl1  <=Rx_mac_sop_tmp;
        Rx_mac_sop          <=Rx_mac_sop_tmp_dl1;
        end
 
 
 
//******************************************************************************
 
duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
.data_a         (Din        ),
.wren_a         (Wr_en      ),
.address_a      (Add_wr     ),
.address_b      (Add_rd     ),
.clock_a        (Clk_MAC    ),
.clock_b        (Clk_SYS    ),
.q_b            (Dout       ));
 
endmodule
 
 
 
 
 

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[/] [srdydrdy_lib/] [trunk/] [external/] [ethernet_tri_mode/] [MAC_rx/] [MAC_rx_FF.v] - Blame information for rev 23

Line No.	Rev	Author	Line
1	23	ghutchis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_FF.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: MAC_rx_FF.v,v $`
42			`// Revision 1.5 2006/06/25 04:58:56 maverickist`
43			`// no message`
44			`//`
45			`// Revision 1.4 2006/05/28 05:09:20 maverickist`
46			`// no message`
47			`//`
48			`// Revision 1.3 2006/01/19 14:07:54 maverickist`
49			`// verification is complete.`
50			`//`
51			`// Revision 1.3 2005/12/16 06:44:16 Administrator`
52			`// replaced tab with space.`
53			`// passed 9.6k length frame test.`
54			`//`
55			`// Revision 1.2 2005/12/13 12:15:37 Administrator`
56			`// no message`
57			`//`
58			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
59			`// no message`
60			`//`
61
62			`module MAC_rx_FF (`
63			`Reset ,`
64			`Clk_MAC ,`
65			`Clk_SYS ,`
66			`//MAC_rx_ctrl interface`
67			`Fifo_data ,`
68			`Fifo_data_en ,`
69			`Fifo_full ,`
70			`Fifo_data_err ,`
71			`Fifo_data_end ,`
72			`//CPU`
73			`Rx_Hwmark,`
74			`Rx_Lwmark,`
75			`RX_APPEND_CRC,`
76			`//user interface`
77			`Rx_mac_ra ,`
78			`Rx_mac_rd ,`
79			`Rx_mac_data ,`
80			`Rx_mac_BE ,`
81			`Rx_mac_sop ,`
82			`Rx_mac_pa,`
83			`Rx_mac_eop`
84			`);`
85			`input Reset ;`
86			`input Clk_MAC ;`
87			`input Clk_SYS ;`
88			`//MAC_rx_ctrl interface`
89			`input [7:0] Fifo_data ;`
90			`input Fifo_data_en ;`
91			`output Fifo_full ;`
92			`input Fifo_data_err ;`
93			`input Fifo_data_end ;`
94			`//CPU`
95			`input RX_APPEND_CRC ;`
96			`input [4:0] Rx_Hwmark ;`
97			`input [4:0] Rx_Lwmark ;`
98			`//user interface`
99			`output Rx_mac_ra ;//`
100			`input Rx_mac_rd ;`
101			`output [31:0] Rx_mac_data ;`
102			`output [1:0] Rx_mac_BE ;`
103			`output Rx_mac_pa ;`
104			`output Rx_mac_sop ;`
105			`output Rx_mac_eop ;`
106
107			`//******************************************************************************`
108			`//internal signals`
109			`//******************************************************************************`
110			`parameter State_byte3 =4'd0;`
111			`parameter State_byte2 =4'd1;`
112			`parameter State_byte1 =4'd2;`
113			`parameter State_byte0 =4'd3;`
114			`parameter State_be0 =4'd4;`
115			`parameter State_be3 =4'd5;`
116			`parameter State_be2 =4'd6;`
117			`parameter State_be1 =4'd7;`
118			`parameter State_err_end =4'd8;`
119			`parameter State_idle =4'd9;`
120
121			`parameter SYS_read =3'd0;`
122			`parameter SYS_pause =3'd1;`
123			`parameter SYS_wait_end =3'd2;`
124			`parameter SYS_idle =3'd3;`
125			`parameter FF_emtpy_err =3'd4;`
126
127			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr;
128			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_ungray;
129			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray;
130			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_gray_dl1;
131			reg [`MAC_TX_FF_DEPTH-1:0] Add_wr_reg;
132
133			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd;
134			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray;
135			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_gray_dl1;
136			reg [`MAC_TX_FF_DEPTH-1:0] Add_rd_ungray;
137			`reg [35:0] Din;`
138			`reg [35:0] Din_tmp;`
139			`reg [35:0] Din_tmp_reg;`
140			`wire[35:0] Dout;`
141			`reg Wr_en;`
142			`reg Wr_en_tmp;`
143			`reg Wr_en_ptr;`
144			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse;
145			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse4;
146			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse3;
147			wire[`MAC_TX_FF_DEPTH-1:0] Add_wr_pluse2;
148			`reg Full;`
149			`reg Almost_full;`
150			`reg Empty /* synthesis syn_keep=1 */;`
151			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
152			`reg [3:0] Next_state;`
153			`reg [7:0] Fifo_data_byte0;`
154			`reg [7:0] Fifo_data_byte1;`
155			`reg [7:0] Fifo_data_byte2;`
156			`reg [7:0] Fifo_data_byte3;`
157			`reg Fifo_data_en_dl1;`
158			`reg [7:0] Fifo_data_dl1;`
159			`reg Rx_mac_sop_tmp ;`
160			`reg Rx_mac_sop ;`
161			`reg Rx_mac_ra ;`
162			`reg Rx_mac_pa ;`
163
164
165
166			`reg [2:0] Current_state_SYS /* synthesis syn_keep=1 */;`
167			`reg [2:0] Next_state_SYS ;`
168			`reg [5:0] Packet_number_inFF /* synthesis syn_keep=1 */;`
169			`reg Packet_number_sub ;`
170			`wire Packet_number_add_edge;`
171			`reg Packet_number_add_dl1;`
172			`reg Packet_number_add_dl2;`
173			`reg Packet_number_add ;`
174			`reg Packet_number_add_tmp ;`
175			`reg Packet_number_add_tmp_dl1;`
176			`reg Packet_number_add_tmp_dl2;`
177
178			`reg Rx_mac_sop_tmp_dl1;`
179			`reg [35:0] Dout_dl1;`
180			`reg [4:0] Fifo_data_count;`
181			`reg Rx_mac_pa_tmp ;`
182			`reg Add_wr_jump_tmp ;`
183			`reg Add_wr_jump_tmp_pl1 ;`
184			`reg Add_wr_jump ;`
185			`reg Add_wr_jump_rd_pl1 ;`
186			`reg [4:0] Rx_Hwmark_pl ;`
187			`reg [4:0] Rx_Lwmark_pl ;`
188			`integer i ;`
189			`//******************************************************************************`
190			`//domain Clk_MAC,write data to dprom.a-port for write`
191			`//******************************************************************************`
192			`always @ (posedge Clk_MAC or posedge Reset)`
193			`if (Reset)`
194			`Current_state <=State_idle;`
195			`else`
196			`Current_state <=Next_state;`
197
198			`always @(Current_state or Fifo_data_en or Fifo_data_err or Fifo_data_end)`
199			`case (Current_state)`
200			`State_idle:`
201			`if (Fifo_data_en)`
202			`Next_state =State_byte3;`
203			`else`
204			`Next_state =Current_state;`
205			`State_byte3:`
206			`if (Fifo_data_en)`
207			`Next_state =State_byte2;`
208			`else if (Fifo_data_err)`
209			`Next_state =State_err_end;`
210			`else if (Fifo_data_end)`
211			`Next_state =State_be1;`
212			`else`
213			`Next_state =Current_state;`
214			`State_byte2:`
215			`if (Fifo_data_en)`
216			`Next_state =State_byte1;`
217			`else if (Fifo_data_err)`
218			`Next_state =State_err_end;`
219			`else if (Fifo_data_end)`
220			`Next_state =State_be2;`
221			`else`
222			`Next_state =Current_state;`
223			`State_byte1:`
224			`if (Fifo_data_en)`
225			`Next_state =State_byte0;`
226			`else if (Fifo_data_err)`
227			`Next_state =State_err_end;`
228			`else if (Fifo_data_end)`
229			`Next_state =State_be3;`
230			`else`
231			`Next_state =Current_state;`
232			`State_byte0:`
233			`if (Fifo_data_en)`
234			`Next_state =State_byte3;`
235			`else if (Fifo_data_err)`
236			`Next_state =State_err_end;`
237			`else if (Fifo_data_end)`
238			`Next_state =State_be0;`
239			`else`
240			`Next_state =Current_state;`
241			`State_be1:`
242			`Next_state =State_idle;`
243			`State_be2:`
244			`Next_state =State_idle;`
245			`State_be3:`
246			`Next_state =State_idle;`
247			`State_be0:`
248			`Next_state =State_idle;`
249			`State_err_end:`
250			`Next_state =State_idle;`
251			`default:`
252			`Next_state =State_idle;`
253			`endcase`
254
255			`//`
256			`always @ (posedge Clk_MAC or posedge Reset)`
257			`if (Reset)`
258			`Add_wr_reg <=0;`
259			`else if (Current_state==State_idle)`
260			`Add_wr_reg <=Add_wr;`
261
262			`//`
263
264
265			`always @ (posedge Reset or posedge Clk_MAC)`
266			`if (Reset)`
267			`Add_wr_gray <=0;`
268			`else`
269			`begin`
270			Add_wr_gray[`MAC_RX_FF_DEPTH-1] <=Add_wr[`MAC_RX_FF_DEPTH-1];
271			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
272			`Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];`
273			`end`
274
275			`//`
276
277			`always @ (posedge Clk_MAC or posedge Reset)`
278			`if (Reset)`
279			`Add_rd_gray_dl1 <=0;`
280			`else`
281			`Add_rd_gray_dl1 <=Add_rd_gray;`
282
283			`always @ (posedge Clk_MAC or posedge Reset)`
284			`if (Reset)`
285			`Add_rd_ungray =0;`
286			`else`
287			`begin`
288			Add_rd_ungray[`MAC_RX_FF_DEPTH-1] =Add_rd_gray_dl1[`MAC_RX_FF_DEPTH-1];
289			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
290			`Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];`
291			`end`
292			`assign Add_wr_pluse=Add_wr+1;`
293			`assign Add_wr_pluse4=Add_wr+4;`
294			`assign Add_wr_pluse3=Add_wr+3;`
295			`assign Add_wr_pluse2=Add_wr+2;`
296
297
298
299			`always @ (posedge Clk_MAC or posedge Reset)`
300			`if (Reset)`
301			`Full <=0;`
302			`else if (Add_wr_pluse==Add_rd_ungray)`
303			`Full <=1;`
304			`else`
305			`Full <=0;`
306
307			`always @ (posedge Clk_MAC or posedge Reset)`
308			`if (Reset)`
309			`Almost_full <=0;`
310			`else if (Add_wr_pluse4==Add_rd_ungray\|\|`
311			`Add_wr_pluse3==Add_rd_ungray\|\|`
312			`Add_wr_pluse2==Add_rd_ungray\|\|`
313			`Add_wr_pluse==Add_rd_ungray`
314			`)`
315			`Almost_full <=1;`
316			`else`
317			`Almost_full <=0;`
318
319			`assign Fifo_full =Almost_full;`
320
321			`//`
322			`always @ (posedge Clk_MAC or posedge Reset)`
323			`if (Reset)`
324			`Add_wr <=0;`
325			`else if (Current_state==State_err_end)`
326			`Add_wr <=Add_wr_reg;`
327			`else if (Wr_en&&!Full)`
328			`Add_wr <=Add_wr +1;`
329
330			`always @ (posedge Clk_MAC or posedge Reset)`
331			`if (Reset)`
332			`Add_wr_jump_tmp <=0;`
333			`else if (Current_state==State_err_end)`
334			`Add_wr_jump_tmp <=1;`
335			`else`
336			`Add_wr_jump_tmp <=0;`
337
338			`always @ (posedge Clk_MAC or posedge Reset)`
339			`if (Reset)`
340			`Add_wr_jump_tmp_pl1 <=0;`
341			`else`
342			`Add_wr_jump_tmp_pl1 <=Add_wr_jump_tmp;`
343
344			`always @ (posedge Clk_MAC or posedge Reset)`
345			`if (Reset)`
346			`Add_wr_jump <=0;`
347			`else if (Current_state==State_err_end)`
348			`Add_wr_jump <=1;`
349			`else if (Add_wr_jump_tmp_pl1)`
350			`Add_wr_jump <=0;`
351
352			`//`
353			`always @ (posedge Clk_MAC or posedge Reset)`
354			`if (Reset)`
355			`Fifo_data_en_dl1 <=0;`
356			`else`
357			`Fifo_data_en_dl1 <=Fifo_data_en;`
358
359			`always @ (posedge Clk_MAC or posedge Reset)`
360			`if (Reset)`
361			`Fifo_data_dl1 <=0;`
362			`else`
363			`Fifo_data_dl1 <=Fifo_data;`
364
365			`always @ (posedge Clk_MAC or posedge Reset)`
366			`if (Reset)`
367			`Fifo_data_byte3 <=0;`
368			`else if (Current_state==State_byte3&&Fifo_data_en_dl1)`
369			`Fifo_data_byte3 <=Fifo_data_dl1;`
370
371			`always @ (posedge Clk_MAC or posedge Reset)`
372			`if (Reset)`
373			`Fifo_data_byte2 <=0;`
374			`else if (Current_state==State_byte2&&Fifo_data_en_dl1)`
375			`Fifo_data_byte2 <=Fifo_data_dl1;`
376
377			`always @ (posedge Clk_MAC or posedge Reset)`
378			`if (Reset)`
379			`Fifo_data_byte1 <=0;`
380			`else if (Current_state==State_byte1&&Fifo_data_en_dl1)`
381			`Fifo_data_byte1 <=Fifo_data_dl1;`
382
383			`always @ (* )`
384			`case (Current_state)`
385			`State_be0:`
386			`Din_tmp ={4'b1000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
387			`State_be1:`
388			`Din_tmp ={4'b1001,Fifo_data_byte3,24'h0};`
389			`State_be2:`
390			`Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};`
391			`State_be3:`
392			`Din_tmp ={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};`
393			`default:`
394			`Din_tmp ={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};`
395			`endcase`
396
397			`always @ (*)`
398			`if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
399			`Current_state==State_be2\|\|Current_state==State_be3\|\|`
400			`(Current_state==State_byte0&&Fifo_data_en))`
401			`Wr_en_tmp =1;`
402			`else`
403			`Wr_en_tmp =0;`
404
405			`always @ (posedge Clk_MAC or posedge Reset)`
406			`if (Reset)`
407			`Din_tmp_reg <=0;`
408			`else if(Wr_en_tmp)`
409			`Din_tmp_reg <=Din_tmp;`
410
411			`always @ (posedge Clk_MAC or posedge Reset)`
412			`if (Reset)`
413			`Wr_en_ptr <=0;`
414			`else if(Current_state==State_idle)`
415			`Wr_en_ptr <=0;`
416			`else if(Wr_en_tmp)`
417			`Wr_en_ptr <=1;`
418
419			`//if not append FCS,delay one cycle write data and Wr_en signal to drop FCS`
420			`always @ (posedge Clk_MAC or posedge Reset)`
421			`if (Reset)`
422			`begin`
423			`Wr_en <=0;`
424			`Din <=0;`
425			`end`
426			`else if(RX_APPEND_CRC)`
427			`begin`
428			`Wr_en <=Wr_en_tmp;`
429			`Din <=Din_tmp;`
430			`end`
431			`else`
432			`begin`
433			`Wr_en <=Wr_en_tmp&&Wr_en_ptr;`
434			`Din <={Din_tmp[35:32],Din_tmp_reg[31:0]};`
435			`end`
436
437			`//this signal for read side to handle the packet number in fifo`
438			`always @ (posedge Clk_MAC or posedge Reset)`
439			`if (Reset)`
440			`Packet_number_add_tmp <=0;`
441			`else if (Current_state==State_be0\|\|Current_state==State_be1\|\|`
442			`Current_state==State_be2\|\|Current_state==State_be3)`
443			`Packet_number_add_tmp <=1;`
444			`else`
445			`Packet_number_add_tmp <=0;`
446
447			`always @ (posedge Clk_MAC or posedge Reset)`
448			`if (Reset)`
449			`begin`
450			`Packet_number_add_tmp_dl1 <=0;`
451			`Packet_number_add_tmp_dl2 <=0;`
452			`end`
453			`else`
454			`begin`
455			`Packet_number_add_tmp_dl1 <=Packet_number_add_tmp;`
456			`Packet_number_add_tmp_dl2 <=Packet_number_add_tmp_dl1;`
457			`end`
458
459			`//Packet_number_add delay to Din[35] is needed to make sure the data have been wroten to ram.`
460			`//expand to two cycles long almost=16 ns`
461			`//if the Clk_SYS period less than 16 ns ,this signal need to expand to 3 or more clock cycles`
462			`always @ (posedge Clk_MAC or posedge Reset)`
463			`if (Reset)`
464			`Packet_number_add <=0;`
465			`else if (Packet_number_add_tmp_dl1\|\|Packet_number_add_tmp_dl2)`
466			`Packet_number_add <=1;`
467			`else`
468			`Packet_number_add <=0;`
469
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492
493			`//******************************************************************************`
494			`//domain Clk_SYS,read data from dprom.b-port for read`
495			`//******************************************************************************`
496
497
498			`always @ (posedge Clk_SYS or posedge Reset)`
499			`if (Reset)`
500			`Current_state_SYS <=SYS_idle;`
501			`else`
502			`Current_state_SYS <=Next_state_SYS;`
503
504			`always @ (Current_state_SYS or Rx_mac_rd or Rx_mac_ra or Dout or Empty)`
505			`case (Current_state_SYS)`
506			`SYS_idle:`
507			`if (Rx_mac_rd&&Rx_mac_ra&&!Empty)`
508			`Next_state_SYS =SYS_read;`
509			`else if(Rx_mac_rd&&Rx_mac_ra&&Empty)`
510			`Next_state_SYS =FF_emtpy_err;`
511			`else`
512			`Next_state_SYS =Current_state_SYS;`
513			`SYS_read:`
514			`if (!Rx_mac_rd)`
515			`Next_state_SYS =SYS_pause;`
516			`else if (Dout[35])`
517			`Next_state_SYS =SYS_wait_end;`
518			`else if (Empty)`
519			`Next_state_SYS =FF_emtpy_err;`
520			`else`
521			`Next_state_SYS =Current_state_SYS;`
522			`SYS_pause:`
523			`if (Rx_mac_rd)`
524			`Next_state_SYS =SYS_read;`
525			`else`
526			`Next_state_SYS =Current_state_SYS;`
527			`FF_emtpy_err:`
528			`if (!Empty)`
529			`Next_state_SYS =SYS_read;`
530			`else`
531			`Next_state_SYS =Current_state_SYS;`
532			`SYS_wait_end:`
533			`if (!Rx_mac_rd)`
534			`Next_state_SYS =SYS_idle;`
535			`else`
536			`Next_state_SYS =Current_state_SYS;`
537			`default:`
538			`Next_state_SYS =SYS_idle;`
539			`endcase`
540
541
542			`//gen Rx_mac_ra`
543			`always @ (posedge Clk_SYS or posedge Reset)`
544			`if (Reset)`
545			`begin`
546			`Packet_number_add_dl1 <=0;`
547			`Packet_number_add_dl2 <=0;`
548			`end`
549			`else`
550			`begin`
551			`Packet_number_add_dl1 <=Packet_number_add;`
552			`Packet_number_add_dl2 <=Packet_number_add_dl1;`
553			`end`
554			`assign Packet_number_add_edge=Packet_number_add_dl1&!Packet_number_add_dl2;`
555
556			`always @ (Current_state_SYS or Next_state_SYS)`
557			`if (Current_state_SYS==SYS_read&&Next_state_SYS==SYS_wait_end)`
558			`Packet_number_sub =1;`
559			`else`
560			`Packet_number_sub =0;`
561
562			`always @ (posedge Clk_SYS or posedge Reset)`
563			`if (Reset)`
564			`Packet_number_inFF <=0;`
565			`else if (Packet_number_add_edge&&!Packet_number_sub)`
566			`Packet_number_inFF <=Packet_number_inFF + 1;`
567			`else if (!Packet_number_add_edge&&Packet_number_sub&&Packet_number_inFF!=0)`
568			`Packet_number_inFF <=Packet_number_inFF - 1;`
569
570			`always @ (posedge Clk_SYS or posedge Reset)`
571			`if (Reset)`
572			`Fifo_data_count <=0;`
573			`else`
574			Fifo_data_count <=Add_wr_ungray[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5]-Add_rd[`MAC_RX_FF_DEPTH-1:`MAC_RX_FF_DEPTH-5];
575
576			`always @ (posedge Clk_SYS or posedge Reset)`
577			`if (Reset)`
578			`begin`
579			`Rx_Hwmark_pl <=0;`
580			`Rx_Lwmark_pl <=0;`
581			`end`
582			`else`
583			`begin`
584			`Rx_Hwmark_pl <=Rx_Hwmark;`
585			`Rx_Lwmark_pl <=Rx_Lwmark;`
586			`end`
587
588			`always @ (posedge Clk_SYS or posedge Reset)`
589			`if (Reset)`
590			`Rx_mac_ra <=0;`
591			`else if (Packet_number_inFF==0&&Fifo_data_count<=Rx_Lwmark_pl)`
592			`Rx_mac_ra <=0;`
593			`else if (Packet_number_inFF>=1\|\|Fifo_data_count>=Rx_Hwmark_pl)`
594			`Rx_mac_ra <=1;`
595
596
597			`//control Add_rd signal;`
598			`always @ (posedge Clk_SYS or posedge Reset)`
599			`if (Reset)`
600			`Add_rd <=0;`
601			`else if (Current_state_SYS==SYS_read&&!Dout[35])`
602			`Add_rd <=Add_rd + 1;`
603
604			`//`
605			`always @ (posedge Reset or posedge Clk_SYS)`
606			`if (Reset)`
607			`Add_rd_gray <=0;`
608			`else`
609			`begin`
610			Add_rd_gray[`MAC_RX_FF_DEPTH-1] <=Add_rd[`MAC_RX_FF_DEPTH-1];
611			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
612			`Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];`
613			`end`
614			`//`
615
616			`always @ (posedge Clk_SYS or posedge Reset)`
617			`if (Reset)`
618			`Add_wr_gray_dl1 <=0;`
619			`else`
620			`Add_wr_gray_dl1 <=Add_wr_gray;`
621
622			`always @ (posedge Clk_SYS or posedge Reset)`
623			`if (Reset)`
624			`Add_wr_jump_rd_pl1 <=0;`
625			`else`
626			`Add_wr_jump_rd_pl1 <=Add_wr_jump;`
627
628			`always @ (posedge Clk_SYS or posedge Reset)`
629			`if (Reset)`
630			`Add_wr_ungray =0;`
631			`else if (!Add_wr_jump_rd_pl1)`
632			`begin`
633			Add_wr_ungray[`MAC_RX_FF_DEPTH-1] =Add_wr_gray_dl1[`MAC_RX_FF_DEPTH-1];
634			for (i=`MAC_RX_FF_DEPTH-2;i>=0;i=i-1)
635			`Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];`
636			`end`
637			`//empty signal gen`
638			`always @ (posedge Clk_SYS or posedge Reset)`
639			`if (Reset)`
640			`Empty <=1;`
641			`else if (Add_rd==Add_wr_ungray)`
642			`Empty <=1;`
643			`else`
644			`Empty <=0;`
645
646
647
648			`always @ (posedge Clk_SYS or posedge Reset)`
649			`if (Reset)`
650			`Dout_dl1 <=0;`
651			`else`
652			`Dout_dl1 <=Dout;`
653
654			`assign Rx_mac_data =Dout_dl1[31:0];`
655			`assign Rx_mac_BE =Dout_dl1[33:32];`
656			`assign Rx_mac_eop =Dout_dl1[35];`
657
658			`//aligned to Addr_rd`
659			`always @ (posedge Clk_SYS or posedge Reset)`
660			`if (Reset)`
661			`Rx_mac_pa_tmp <=0;`
662			`else if (Current_state_SYS==SYS_read&&!Dout[35])`
663			`Rx_mac_pa_tmp <=1;`
664			`else`
665			`Rx_mac_pa_tmp <=0;`
666
667
668
669			`always @ (posedge Clk_SYS or posedge Reset)`
670			`if (Reset)`
671			`Rx_mac_pa <=0;`
672			`else`
673			`Rx_mac_pa <=Rx_mac_pa_tmp;`
674
675
676
677			`always @ (posedge Clk_SYS or posedge Reset)`
678			`if (Reset)`
679			`Rx_mac_sop_tmp <=0;`
680			`else if (Current_state_SYS==SYS_idle&&Next_state_SYS==SYS_read)`
681			`Rx_mac_sop_tmp <=1;`
682			`else`
683			`Rx_mac_sop_tmp <=0;`
684
685
686
687			`always @ (posedge Clk_SYS or posedge Reset)`
688			`if (Reset)`
689			`begin`
690			`Rx_mac_sop_tmp_dl1 <=0;`
691			`Rx_mac_sop <=0;`
692			`end`
693			`else`
694			`begin`
695			`Rx_mac_sop_tmp_dl1 <=Rx_mac_sop_tmp;`
696			`Rx_mac_sop <=Rx_mac_sop_tmp_dl1;`
697			`end`
698
699
700
701			`//******************************************************************************`
702
703			duram #(36,`MAC_RX_FF_DEPTH,"M4K") U_duram(
704			`.data_a (Din ),`
705			`.wren_a (Wr_en ),`
706			`.address_a (Add_wr ),`
707			`.address_b (Add_rd ),`
708			`.clock_a (Clk_MAC ),`
709			`.clock_b (Clk_SYS ),`
710			`.q_b (Dout ));`
711
712			`endmodule`
713
714
715
716
717