URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [external/] [ethernet_tri_mode/] [MAC_rx/] [MAC_rx_ctrl.v] - Blame information for rev 23

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MAC_rx_ctrl.v                                               ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao (gaojon@yahoo.com)                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: MAC_rx_ctrl.v,v $
// Revision 1.4  2006/06/25 04:58:56  maverickist
// no message
//
// Revision 1.3  2006/01/19 14:07:54  maverickist
// verification is complete.
//
// Revision 1.3  2005/12/16 06:44:17  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.2  2005/12/13 12:15:37  Administrator
// no message
//
// Revision 1.1.1.1  2005/12/13 01:51:45  Administrator
// no message
//                                           
 
module MAC_rx_ctrl (
Reset   ,
Clk     ,
//RMII interface                                    
MCrs_dv ,       //
MRxD    ,       //  
MRxErr  ,       //  
//CRC_chk interface                                 
CRC_en    ,
CRC_init  ,
CRC_err  ,
//MAC_rx_add_chk interface                          
MAC_add_en          ,
MAC_rx_add_chk_err  ,
//broadcast_filter     
broadcast_ptr   ,
broadcast_drop  ,
//flow_control signals      
pause_quanta        ,
pause_quanta_val    ,
//MAC_rx_FF interface                               
Fifo_data       ,
Fifo_data_en    ,
Fifo_data_err   ,
Fifo_data_end   ,
Fifo_full       ,
//RMON interface                
Rx_pkt_type_rmon        ,
Rx_pkt_length_rmon      ,
Rx_apply_rmon           ,
Rx_pkt_err_type_rmon    ,
//CPU                                         
RX_IFG_SET    ,
RX_MAX_LENGTH,
RX_MIN_LENGTH
);
 
input           Reset   ;
input           Clk     ;
                //RMII interface  
input           MCrs_dv ;
input   [7:0]   MRxD    ;
input           MRxErr  ;
                //CRC_chk interface
output          CRC_en  ;
output          CRC_init;
input           CRC_err ;
                //MAC_rx_add_chk interface
output          MAC_add_en          ;
input           MAC_rx_add_chk_err  ;
                //broadcast_filter
output          broadcast_ptr           ;
input           broadcast_drop          ;
                //flow_control signals  
output  [15:0]  pause_quanta        ;
output          pause_quanta_val    ;
                //MAC_rx_FF interface
output  [7:0]   Fifo_data       ;
output          Fifo_data_en    ;
output          Fifo_data_err   ;
output          Fifo_data_end   ;
input           Fifo_full;
                //RMON interface
output  [15:0]  Rx_pkt_length_rmon      ;
output          Rx_apply_rmon           ;
output  [2:0]   Rx_pkt_err_type_rmon    ;
output  [2:0]   Rx_pkt_type_rmon        ;
                //CPU
input   [5:0]   RX_IFG_SET    ;
input   [15:0]  RX_MAX_LENGTH   ;// 1518
input   [6:0]   RX_MIN_LENGTH   ;// 64
 
//******************************************************************************
//internal signals
//******************************************************************************
parameter       State_idle          =4'd00;
parameter       State_preamble      =4'd01;
parameter       State_SFD           =4'd02;
parameter       State_data          =4'd03;
parameter       State_checkCRC      =4'd04;
parameter       State_OkEnd         =4'd07;
parameter       State_drop          =4'd08;
parameter       State_ErrEnd        =4'd09;
parameter       State_CRCErrEnd     =4'd10;
parameter       State_FFFullDrop    =4'd11;
parameter       State_FFFullErrEnd  =4'd12;
parameter       State_IFG           =4'd13;
 
parameter       Pause_idle          =4'd0;
parameter       Pause_pre_syn       =4'd1;
parameter       Pause_quanta_hi     =4'd2;
parameter       Pause_quanta_lo     =4'd3;
parameter       Pause_syn           =4'd4;
 
reg [3:0]       Current_state /* synthesis syn_keep=1 */;
reg [3:0]       Next_state;
reg [3:0]       Pause_current /* synthesis syn_keep=1 */;
reg [3:0]       Pause_next;
reg [5:0]       IFG_counter;
reg             Crs_dv  ;
reg [7:0]       RxD ;
reg [7:0]       RxD_dl1 ;
reg             RxErr   ;
reg [15:0]      Frame_length_counter;
reg             Too_long;
reg             Too_short;
reg             Fifo_data_en;
reg             Fifo_data_end;
reg             Fifo_data_err;
reg             CRC_en;
reg             CRC_init;
reg             Rx_apply_rmon;
reg             Rx_apply_rmon_tmp;
reg             Rx_apply_rmon_tmp_pl1;
reg [2:0]       Rx_pkt_err_type_rmon;
reg             MAC_add_en;
reg [2:0]       Rx_pkt_type_rmon;
reg [7:0]       pause_quanta_h      ;
reg [15:0]      pause_quanta        ;
reg             pause_quanta_val    ;
reg             pause_quanta_val_tmp;
reg             pause_frame_ptr     ;
reg             broadcast_ptr           ;
//******************************************************************************
//delay signals                                                          
//******************************************************************************
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        begin
            Crs_dv      <=0;
            RxD         <=0;
            RxErr       <=0;
        end
    else
        begin
            Crs_dv      <=MCrs_dv   ;
            RxD         <=MRxD      ;
            RxErr       <=MRxErr    ;
        end
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        RxD_dl1     <=0;
    else
        RxD_dl1     <=RxD;
 
//******************************************************************************
//State_machine                                                           
//******************************************************************************
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        Current_state   <=State_idle;
    else
        Current_state   <=Next_state;
 
always @ (*)
        case (Current_state)
            State_idle:
                    if (Crs_dv&&RxD==8'h55)
                        Next_state  =State_preamble;
                    else
                        Next_state  =Current_state;
            State_preamble:
                    if (!Crs_dv)
                        Next_state  =State_ErrEnd;
                    else if (RxErr)
                        Next_state  =State_drop;
                    else if (RxD==8'hd5)
                        Next_state  =State_SFD;
                    else if (RxD==8'h55)
                        Next_state  =Current_state;
                    else
                        Next_state  =State_drop;
            State_SFD:
                    if (!Crs_dv)
                        Next_state  =State_ErrEnd;
                    else if (RxErr)
                        Next_state  =State_drop;
                    else
                        Next_state  =State_data;
            State_data:
                    if (!Crs_dv&&!Too_short&&!Too_long)
                        Next_state  =State_checkCRC;
                    else if (!Crs_dv&&(Too_short||Too_long))
                        Next_state  =State_ErrEnd;
                    else if (Fifo_full)
                        Next_state  =State_FFFullErrEnd;
                    else if (RxErr||MAC_rx_add_chk_err||Too_long||broadcast_drop)
                        Next_state  =State_drop;
                    else
                        Next_state  =State_data;
            State_checkCRC:
                     if (CRC_err)
                        Next_state  =State_CRCErrEnd;
                     else
                        Next_state  =State_OkEnd;
            State_drop:
                    if (!Crs_dv)
                        Next_state  =State_ErrEnd;
                    else
                        Next_state  =Current_state;
            State_OkEnd:
                        Next_state  =State_IFG;
            State_ErrEnd:
                        Next_state  =State_IFG;
 
            State_CRCErrEnd:
                        Next_state  =State_IFG;
            State_FFFullDrop:
                    if (!Crs_dv)
                        Next_state  =State_IFG;
                    else
                        Next_state  =Current_state;
            State_FFFullErrEnd:
                        Next_state  =State_FFFullDrop;
            State_IFG:
                    if (IFG_counter==RX_IFG_SET-4)   //remove some additional time     
                        Next_state  =State_idle;
                    else
                        Next_state  =Current_state;
 
            default:
                        Next_state  =State_idle;
        endcase
 
 
always @ (posedge Reset or posedge Clk)
    if (Reset)
        IFG_counter     <=0;
    else if (Current_state!=State_IFG)
        IFG_counter     <=0;
    else
        IFG_counter     <=IFG_counter + 1;
//******************************************************************************
//gen fifo interface signals                                                     
//******************************************************************************                     
 
assign  Fifo_data   =RxD_dl1;
 
always @(Current_state)
    if  (Current_state==State_data)
        Fifo_data_en        =1;
    else
        Fifo_data_en        =0;
 
always @(Current_state)
    if  (Current_state==State_ErrEnd||Current_state==State_OkEnd
         ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Fifo_data_end       =1;
    else
        Fifo_data_end       =0;
 
always @(Current_state)
    if  (Current_state==State_ErrEnd||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Fifo_data_err       =1;
    else
        Fifo_data_err       =0;
 
//******************************************************************************
//CRC_chk interface                                               
//****************************************************************************** 
 
always @(Current_state)
    if (Current_state==State_data)
        CRC_en  =1;
    else
        CRC_en  =0;
 
always @(Current_state)
    if (Current_state==State_SFD)
        CRC_init    =1;
    else
        CRC_init    =0;
 
//******************************************************************************
//gen rmon signals                                         
//******************************************************************************    
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Frame_length_counter        <=0;
    else if (Current_state==State_SFD)
        Frame_length_counter        <=1;
    else if (Current_state==State_data)
        Frame_length_counter        <=Frame_length_counter+ 1'b1;
 
always @ (Frame_length_counter or RX_MIN_LENGTH)
    if (Frame_length_counter<RX_MIN_LENGTH)
        Too_short   =1;
    else
        Too_short   =0;
 
always @ (*)
    if (Frame_length_counter>RX_MAX_LENGTH)
        Too_long    =1;
    else
        Too_long    =0;
 
assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon_tmp   <=0;
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon_tmp   <=1;
    else
        Rx_apply_rmon_tmp   <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon_tmp_pl1   <=0;
    else
        Rx_apply_rmon_tmp_pl1   <=Rx_apply_rmon_tmp;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_apply_rmon   <=0;
    else if (Current_state==State_OkEnd||Current_state==State_ErrEnd
        ||Current_state==State_CRCErrEnd||Current_state==State_FFFullErrEnd)
        Rx_apply_rmon   <=1;
    else if (Rx_apply_rmon_tmp_pl1)
        Rx_apply_rmon   <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_pkt_err_type_rmon    <=0;
    else if (Current_state==State_CRCErrEnd)
        Rx_pkt_err_type_rmon    <=3'b001    ;//
    else if (Current_state==State_FFFullErrEnd)
        Rx_pkt_err_type_rmon    <=3'b010    ;// 
    else if (Current_state==State_ErrEnd)
        Rx_pkt_err_type_rmon    <=3'b011    ;//
    else if(Current_state==State_OkEnd)
        Rx_pkt_err_type_rmon    <=3'b100    ;
 
 
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Rx_pkt_type_rmon        <=0;
    else if (Current_state==State_OkEnd&&pause_frame_ptr)
        Rx_pkt_type_rmon        <=3'b100    ;//
    else if(Current_state==State_SFD&&Next_state==State_data)
        Rx_pkt_type_rmon        <={1'b0,MRxD[7:6]};
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        broadcast_ptr   <=0;
    else if(Current_state==State_IFG)
        broadcast_ptr   <=0;
    else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)
        broadcast_ptr   <=1;
 
 
 
//******************************************************************************
//MAC add checker signals                                                              
//******************************************************************************
always @ (Frame_length_counter or Fifo_data_en)
    if(Frame_length_counter>=1&&Frame_length_counter<=6)
        MAC_add_en  <=Fifo_data_en;
    else
        MAC_add_en  <=0;
 
//******************************************************************************
//flow control signals                                                            
//******************************************************************************
always @ (posedge Clk or posedge Reset)
    if (Reset)
        Pause_current   <=Pause_idle;
    else
        Pause_current   <=Pause_next;
 
always @ (*)
    case (Pause_current)
        Pause_idle  :
            if(Current_state==State_SFD)
                Pause_next  =Pause_pre_syn;
            else
                Pause_next  =Pause_current;
        Pause_pre_syn:
            case (Frame_length_counter)
                16'd1:  if (RxD_dl1==8'h01)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd2:  if (RxD_dl1==8'h80)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd3:  if (RxD_dl1==8'hc2)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd4:  if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd5:  if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd6:  if (RxD_dl1==8'h01)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd13: if (RxD_dl1==8'h88)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd14: if (RxD_dl1==8'h08)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd15: if (RxD_dl1==8'h00)
                            Pause_next  =Pause_current;
                        else
                            Pause_next  =Pause_idle;
                16'd16: if (RxD_dl1==8'h01)
                            Pause_next  =Pause_quanta_hi;
                        else
                            Pause_next  =Pause_idle;
                default:    Pause_next  =Pause_current;
            endcase
        Pause_quanta_hi :
            Pause_next  =Pause_quanta_lo;
        Pause_quanta_lo :
            Pause_next  =Pause_syn;
        Pause_syn       :
            if (Current_state==State_IFG)
                Pause_next  =Pause_idle;
            else
                Pause_next  =Pause_current;
        default
            Pause_next  =Pause_idle;
    endcase
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_h      <=0;
    else if(Pause_current==Pause_quanta_hi)
        pause_quanta_h      <=RxD_dl1;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta        <=0;
    else if(Pause_current==Pause_quanta_lo)
        pause_quanta        <={pause_quanta_h,RxD_dl1};
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_val_tmp    <=0;
    else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)
        pause_quanta_val_tmp    <=1;
    else
        pause_quanta_val_tmp    <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_quanta_val    <=0;
    else if(Current_state==State_OkEnd&&Pause_current==Pause_syn||pause_quanta_val_tmp)
        pause_quanta_val    <=1;
    else
        pause_quanta_val    <=0;
 
always @ (posedge Clk or posedge Reset)
    if (Reset)
        pause_frame_ptr     <=0;
    else if(Pause_current==Pause_syn)
        pause_frame_ptr     <=1;
    else
        pause_frame_ptr     <=0;
 
endmodule
 
 

Browse

Tools

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [external/] [ethernet_tri_mode/] [MAC_rx/] [MAC_rx_ctrl.v] - Blame information for rev 23

Line No.	Rev	Author	Line
1	23	ghutchis	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MAC_rx_ctrl.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Jon Gao (gaojon@yahoo.com) ////`
10			`//// ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2001 Authors ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38			`//`
39			`// CVS Revision History`
40			`//`
41			`// $Log: MAC_rx_ctrl.v,v $`
42			`// Revision 1.4 2006/06/25 04:58:56 maverickist`
43			`// no message`
44			`//`
45			`// Revision 1.3 2006/01/19 14:07:54 maverickist`
46			`// verification is complete.`
47			`//`
48			`// Revision 1.3 2005/12/16 06:44:17 Administrator`
49			`// replaced tab with space.`
50			`// passed 9.6k length frame test.`
51			`//`
52			`// Revision 1.2 2005/12/13 12:15:37 Administrator`
53			`// no message`
54			`//`
55			`// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator`
56			`// no message`
57			`//`
58
59			`module MAC_rx_ctrl (`
60			`Reset ,`
61			`Clk ,`
62			`//RMII interface`
63			`MCrs_dv , //`
64			`MRxD , //`
65			`MRxErr , //`
66			`//CRC_chk interface`
67			`CRC_en ,`
68			`CRC_init ,`
69			`CRC_err ,`
70			`//MAC_rx_add_chk interface`
71			`MAC_add_en ,`
72			`MAC_rx_add_chk_err ,`
73			`//broadcast_filter`
74			`broadcast_ptr ,`
75			`broadcast_drop ,`
76			`//flow_control signals`
77			`pause_quanta ,`
78			`pause_quanta_val ,`
79			`//MAC_rx_FF interface`
80			`Fifo_data ,`
81			`Fifo_data_en ,`
82			`Fifo_data_err ,`
83			`Fifo_data_end ,`
84			`Fifo_full ,`
85			`//RMON interface`
86			`Rx_pkt_type_rmon ,`
87			`Rx_pkt_length_rmon ,`
88			`Rx_apply_rmon ,`
89			`Rx_pkt_err_type_rmon ,`
90			`//CPU`
91			`RX_IFG_SET ,`
92			`RX_MAX_LENGTH,`
93			`RX_MIN_LENGTH`
94			`);`
95
96			`input Reset ;`
97			`input Clk ;`
98			`//RMII interface`
99			`input MCrs_dv ;`
100			`input [7:0] MRxD ;`
101			`input MRxErr ;`
102			`//CRC_chk interface`
103			`output CRC_en ;`
104			`output CRC_init;`
105			`input CRC_err ;`
106			`//MAC_rx_add_chk interface`
107			`output MAC_add_en ;`
108			`input MAC_rx_add_chk_err ;`
109			`//broadcast_filter`
110			`output broadcast_ptr ;`
111			`input broadcast_drop ;`
112			`//flow_control signals`
113			`output [15:0] pause_quanta ;`
114			`output pause_quanta_val ;`
115			`//MAC_rx_FF interface`
116			`output [7:0] Fifo_data ;`
117			`output Fifo_data_en ;`
118			`output Fifo_data_err ;`
119			`output Fifo_data_end ;`
120			`input Fifo_full;`
121			`//RMON interface`
122			`output [15:0] Rx_pkt_length_rmon ;`
123			`output Rx_apply_rmon ;`
124			`output [2:0] Rx_pkt_err_type_rmon ;`
125			`output [2:0] Rx_pkt_type_rmon ;`
126			`//CPU`
127			`input [5:0] RX_IFG_SET ;`
128			`input [15:0] RX_MAX_LENGTH ;// 1518`
129			`input [6:0] RX_MIN_LENGTH ;// 64`
130
131			`//******************************************************************************`
132			`//internal signals`
133			`//******************************************************************************`
134			`parameter State_idle =4'd00;`
135			`parameter State_preamble =4'd01;`
136			`parameter State_SFD =4'd02;`
137			`parameter State_data =4'd03;`
138			`parameter State_checkCRC =4'd04;`
139			`parameter State_OkEnd =4'd07;`
140			`parameter State_drop =4'd08;`
141			`parameter State_ErrEnd =4'd09;`
142			`parameter State_CRCErrEnd =4'd10;`
143			`parameter State_FFFullDrop =4'd11;`
144			`parameter State_FFFullErrEnd =4'd12;`
145			`parameter State_IFG =4'd13;`
146
147			`parameter Pause_idle =4'd0;`
148			`parameter Pause_pre_syn =4'd1;`
149			`parameter Pause_quanta_hi =4'd2;`
150			`parameter Pause_quanta_lo =4'd3;`
151			`parameter Pause_syn =4'd4;`
152
153			`reg [3:0] Current_state /* synthesis syn_keep=1 */;`
154			`reg [3:0] Next_state;`
155			`reg [3:0] Pause_current /* synthesis syn_keep=1 */;`
156			`reg [3:0] Pause_next;`
157			`reg [5:0] IFG_counter;`
158			`reg Crs_dv ;`
159			`reg [7:0] RxD ;`
160			`reg [7:0] RxD_dl1 ;`
161			`reg RxErr ;`
162			`reg [15:0] Frame_length_counter;`
163			`reg Too_long;`
164			`reg Too_short;`
165			`reg Fifo_data_en;`
166			`reg Fifo_data_end;`
167			`reg Fifo_data_err;`
168			`reg CRC_en;`
169			`reg CRC_init;`
170			`reg Rx_apply_rmon;`
171			`reg Rx_apply_rmon_tmp;`
172			`reg Rx_apply_rmon_tmp_pl1;`
173			`reg [2:0] Rx_pkt_err_type_rmon;`
174			`reg MAC_add_en;`
175			`reg [2:0] Rx_pkt_type_rmon;`
176			`reg [7:0] pause_quanta_h ;`
177			`reg [15:0] pause_quanta ;`
178			`reg pause_quanta_val ;`
179			`reg pause_quanta_val_tmp;`
180			`reg pause_frame_ptr ;`
181			`reg broadcast_ptr ;`
182			`//******************************************************************************`
183			`//delay signals`
184			`//******************************************************************************`
185
186			`always @ (posedge Reset or posedge Clk)`
187			`if (Reset)`
188			`begin`
189			`Crs_dv <=0;`
190			`RxD <=0;`
191			`RxErr <=0;`
192			`end`
193			`else`
194			`begin`
195			`Crs_dv <=MCrs_dv ;`
196			`RxD <=MRxD ;`
197			`RxErr <=MRxErr ;`
198			`end`
199
200			`always @ (posedge Reset or posedge Clk)`
201			`if (Reset)`
202			`RxD_dl1 <=0;`
203			`else`
204			`RxD_dl1 <=RxD;`
205
206			`//******************************************************************************`
207			`//State_machine`
208			`//******************************************************************************`
209
210			`always @ (posedge Reset or posedge Clk)`
211			`if (Reset)`
212			`Current_state <=State_idle;`
213			`else`
214			`Current_state <=Next_state;`
215
216			`always @ (*)`
217			`case (Current_state)`
218			`State_idle:`
219			`if (Crs_dv&&RxD==8'h55)`
220			`Next_state =State_preamble;`
221			`else`
222			`Next_state =Current_state;`
223			`State_preamble:`
224			`if (!Crs_dv)`
225			`Next_state =State_ErrEnd;`
226			`else if (RxErr)`
227			`Next_state =State_drop;`
228			`else if (RxD==8'hd5)`
229			`Next_state =State_SFD;`
230			`else if (RxD==8'h55)`
231			`Next_state =Current_state;`
232			`else`
233			`Next_state =State_drop;`
234			`State_SFD:`
235			`if (!Crs_dv)`
236			`Next_state =State_ErrEnd;`
237			`else if (RxErr)`
238			`Next_state =State_drop;`
239			`else`
240			`Next_state =State_data;`
241			`State_data:`
242			`if (!Crs_dv&&!Too_short&&!Too_long)`
243			`Next_state =State_checkCRC;`
244			`else if (!Crs_dv&&(Too_short\|\|Too_long))`
245			`Next_state =State_ErrEnd;`
246			`else if (Fifo_full)`
247			`Next_state =State_FFFullErrEnd;`
248			`else if (RxErr\|\|MAC_rx_add_chk_err\|\|Too_long\|\|broadcast_drop)`
249			`Next_state =State_drop;`
250			`else`
251			`Next_state =State_data;`
252			`State_checkCRC:`
253			`if (CRC_err)`
254			`Next_state =State_CRCErrEnd;`
255			`else`
256			`Next_state =State_OkEnd;`
257			`State_drop:`
258			`if (!Crs_dv)`
259			`Next_state =State_ErrEnd;`
260			`else`
261			`Next_state =Current_state;`
262			`State_OkEnd:`
263			`Next_state =State_IFG;`
264			`State_ErrEnd:`
265			`Next_state =State_IFG;`
266
267			`State_CRCErrEnd:`
268			`Next_state =State_IFG;`
269			`State_FFFullDrop:`
270			`if (!Crs_dv)`
271			`Next_state =State_IFG;`
272			`else`
273			`Next_state =Current_state;`
274			`State_FFFullErrEnd:`
275			`Next_state =State_FFFullDrop;`
276			`State_IFG:`
277			`if (IFG_counter==RX_IFG_SET-4) //remove some additional time`
278			`Next_state =State_idle;`
279			`else`
280			`Next_state =Current_state;`
281
282			`default:`
283			`Next_state =State_idle;`
284			`endcase`
285
286
287			`always @ (posedge Reset or posedge Clk)`
288			`if (Reset)`
289			`IFG_counter <=0;`
290			`else if (Current_state!=State_IFG)`
291			`IFG_counter <=0;`
292			`else`
293			`IFG_counter <=IFG_counter + 1;`
294			`//******************************************************************************`
295			`//gen fifo interface signals`
296			`//******************************************************************************`
297
298			`assign Fifo_data =RxD_dl1;`
299
300			`always @(Current_state)`
301			`if (Current_state==State_data)`
302			`Fifo_data_en =1;`
303			`else`
304			`Fifo_data_en =0;`
305
306			`always @(Current_state)`
307			`if (Current_state==State_ErrEnd\|\|Current_state==State_OkEnd`
308			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
309			`Fifo_data_end =1;`
310			`else`
311			`Fifo_data_end =0;`
312
313			`always @(Current_state)`
314			`if (Current_state==State_ErrEnd\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
315			`Fifo_data_err =1;`
316			`else`
317			`Fifo_data_err =0;`
318
319			`//******************************************************************************`
320			`//CRC_chk interface`
321			`//******************************************************************************`
322
323			`always @(Current_state)`
324			`if (Current_state==State_data)`
325			`CRC_en =1;`
326			`else`
327			`CRC_en =0;`
328
329			`always @(Current_state)`
330			`if (Current_state==State_SFD)`
331			`CRC_init =1;`
332			`else`
333			`CRC_init =0;`
334
335			`//******************************************************************************`
336			`//gen rmon signals`
337			`//******************************************************************************`
338			`always @ (posedge Clk or posedge Reset)`
339			`if (Reset)`
340			`Frame_length_counter <=0;`
341			`else if (Current_state==State_SFD)`
342			`Frame_length_counter <=1;`
343			`else if (Current_state==State_data)`
344			`Frame_length_counter <=Frame_length_counter+ 1'b1;`
345
346			`always @ (Frame_length_counter or RX_MIN_LENGTH)`
347			`if (Frame_length_counter<RX_MIN_LENGTH)`
348			`Too_short =1;`
349			`else`
350			`Too_short =0;`
351
352			`always @ (*)`
353			`if (Frame_length_counter>RX_MAX_LENGTH)`
354			`Too_long =1;`
355			`else`
356			`Too_long =0;`
357
358			`assign Rx_pkt_length_rmon=Frame_length_counter-1'b1;`
359
360			`always @ (posedge Clk or posedge Reset)`
361			`if (Reset)`
362			`Rx_apply_rmon_tmp <=0;`
363			`else if (Current_state==State_OkEnd\|\|Current_state==State_ErrEnd`
364			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
365			`Rx_apply_rmon_tmp <=1;`
366			`else`
367			`Rx_apply_rmon_tmp <=0;`
368
369			`always @ (posedge Clk or posedge Reset)`
370			`if (Reset)`
371			`Rx_apply_rmon_tmp_pl1 <=0;`
372			`else`
373			`Rx_apply_rmon_tmp_pl1 <=Rx_apply_rmon_tmp;`
374
375			`always @ (posedge Clk or posedge Reset)`
376			`if (Reset)`
377			`Rx_apply_rmon <=0;`
378			`else if (Current_state==State_OkEnd\|\|Current_state==State_ErrEnd`
379			`\|\|Current_state==State_CRCErrEnd\|\|Current_state==State_FFFullErrEnd)`
380			`Rx_apply_rmon <=1;`
381			`else if (Rx_apply_rmon_tmp_pl1)`
382			`Rx_apply_rmon <=0;`
383
384			`always @ (posedge Clk or posedge Reset)`
385			`if (Reset)`
386			`Rx_pkt_err_type_rmon <=0;`
387			`else if (Current_state==State_CRCErrEnd)`
388			`Rx_pkt_err_type_rmon <=3'b001 ;//`
389			`else if (Current_state==State_FFFullErrEnd)`
390			`Rx_pkt_err_type_rmon <=3'b010 ;//`
391			`else if (Current_state==State_ErrEnd)`
392			`Rx_pkt_err_type_rmon <=3'b011 ;//`
393			`else if(Current_state==State_OkEnd)`
394			`Rx_pkt_err_type_rmon <=3'b100 ;`
395
396
397
398			`always @ (posedge Clk or posedge Reset)`
399			`if (Reset)`
400			`Rx_pkt_type_rmon <=0;`
401			`else if (Current_state==State_OkEnd&&pause_frame_ptr)`
402			`Rx_pkt_type_rmon <=3'b100 ;//`
403			`else if(Current_state==State_SFD&&Next_state==State_data)`
404			`Rx_pkt_type_rmon <={1'b0,MRxD[7:6]};`
405
406			`always @ (posedge Clk or posedge Reset)`
407			`if (Reset)`
408			`broadcast_ptr <=0;`
409			`else if(Current_state==State_IFG)`
410			`broadcast_ptr <=0;`
411			`else if(Current_state==State_SFD&&Next_state==State_data&&MRxD[7:6]==2'b11)`
412			`broadcast_ptr <=1;`
413
414
415
416			`//******************************************************************************`
417			`//MAC add checker signals`
418			`//******************************************************************************`
419			`always @ (Frame_length_counter or Fifo_data_en)`
420			`if(Frame_length_counter>=1&&Frame_length_counter<=6)`
421			`MAC_add_en <=Fifo_data_en;`
422			`else`
423			`MAC_add_en <=0;`
424
425			`//******************************************************************************`
426			`//flow control signals`
427			`//******************************************************************************`
428			`always @ (posedge Clk or posedge Reset)`
429			`if (Reset)`
430			`Pause_current <=Pause_idle;`
431			`else`
432			`Pause_current <=Pause_next;`
433
434			`always @ (*)`
435			`case (Pause_current)`
436			`Pause_idle :`
437			`if(Current_state==State_SFD)`
438			`Pause_next =Pause_pre_syn;`
439			`else`
440			`Pause_next =Pause_current;`
441			`Pause_pre_syn:`
442			`case (Frame_length_counter)`
443			`16'd1: if (RxD_dl1==8'h01)`
444			`Pause_next =Pause_current;`
445			`else`
446			`Pause_next =Pause_idle;`
447			`16'd2: if (RxD_dl1==8'h80)`
448			`Pause_next =Pause_current;`
449			`else`
450			`Pause_next =Pause_idle;`
451			`16'd3: if (RxD_dl1==8'hc2)`
452			`Pause_next =Pause_current;`
453			`else`
454			`Pause_next =Pause_idle;`
455			`16'd4: if (RxD_dl1==8'h00)`
456			`Pause_next =Pause_current;`
457			`else`
458			`Pause_next =Pause_idle;`
459			`16'd5: if (RxD_dl1==8'h00)`
460			`Pause_next =Pause_current;`
461			`else`
462			`Pause_next =Pause_idle;`
463			`16'd6: if (RxD_dl1==8'h01)`
464			`Pause_next =Pause_current;`
465			`else`
466			`Pause_next =Pause_idle;`
467			`16'd13: if (RxD_dl1==8'h88)`
468			`Pause_next =Pause_current;`
469			`else`
470			`Pause_next =Pause_idle;`
471			`16'd14: if (RxD_dl1==8'h08)`
472			`Pause_next =Pause_current;`
473			`else`
474			`Pause_next =Pause_idle;`
475			`16'd15: if (RxD_dl1==8'h00)`
476			`Pause_next =Pause_current;`
477			`else`
478			`Pause_next =Pause_idle;`
479			`16'd16: if (RxD_dl1==8'h01)`
480			`Pause_next =Pause_quanta_hi;`
481			`else`
482			`Pause_next =Pause_idle;`
483			`default: Pause_next =Pause_current;`
484			`endcase`
485			`Pause_quanta_hi :`
486			`Pause_next =Pause_quanta_lo;`
487			`Pause_quanta_lo :`
488			`Pause_next =Pause_syn;`
489			`Pause_syn :`
490			`if (Current_state==State_IFG)`
491			`Pause_next =Pause_idle;`
492			`else`
493			`Pause_next =Pause_current;`
494			`default`
495			`Pause_next =Pause_idle;`
496			`endcase`
497
498			`always @ (posedge Clk or posedge Reset)`
499			`if (Reset)`
500			`pause_quanta_h <=0;`
501			`else if(Pause_current==Pause_quanta_hi)`
502			`pause_quanta_h <=RxD_dl1;`
503
504			`always @ (posedge Clk or posedge Reset)`
505			`if (Reset)`
506			`pause_quanta <=0;`
507			`else if(Pause_current==Pause_quanta_lo)`
508			`pause_quanta <={pause_quanta_h,RxD_dl1};`
509
510			`always @ (posedge Clk or posedge Reset)`
511			`if (Reset)`
512			`pause_quanta_val_tmp <=0;`
513			`else if(Current_state==State_OkEnd&&Pause_current==Pause_syn)`
514			`pause_quanta_val_tmp <=1;`
515			`else`
516			`pause_quanta_val_tmp <=0;`
517
518			`always @ (posedge Clk or posedge Reset)`
519			`if (Reset)`
520			`pause_quanta_val <=0;`
521			`else if(Current_state==State_OkEnd&&Pause_current==Pause_syn\|\|pause_quanta_val_tmp)`
522			`pause_quanta_val <=1;`
523			`else`
524			`pause_quanta_val <=0;`
525
526			`always @ (posedge Clk or posedge Reset)`
527			`if (Reset)`
528			`pause_frame_ptr <=0;`
529			`else if(Pause_current==Pause_syn)`
530			`pause_frame_ptr <=1;`
531			`else`
532			`pause_frame_ptr <=0;`
533
534			`endmodule`
535
536