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//////////////////////////////////////////////////////////////////////
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//// ////
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//// RMON.v ////
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//// ////
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//// This file is part of the Ethernet IP core project ////
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//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
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//// ////
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//// Author(s): ////
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//// - Jon Gao (gaojon@yahoo.com) ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2001 Authors ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: RMON.v,v $
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// Revision 1.4 2006/06/25 04:58:56 maverickist
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// no message
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//
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// Revision 1.3 2006/01/19 14:07:53 maverickist
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// verification is complete.
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//
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// Revision 1.2 2005/12/16 06:44:16 Administrator
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// replaced tab with space.
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// passed 9.6k length frame test.
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//
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// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
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// no message
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//
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module RMON (
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Clk ,
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Reset ,
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//Tx_RMON
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Tx_pkt_type_rmon ,
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Tx_pkt_length_rmon ,
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Tx_apply_rmon ,
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Tx_pkt_err_type_rmon,
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//Tx_RMON
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Rx_pkt_type_rmon ,
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Rx_pkt_length_rmon ,
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Rx_apply_rmon ,
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Rx_pkt_err_type_rmon,
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//CPU
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CPU_rd_addr ,
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CPU_rd_apply ,
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CPU_rd_grant ,
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CPU_rd_dout
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);
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input Clk ;
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input Reset ;
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//Tx_RMON
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input [2:0] Tx_pkt_type_rmon ;
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input [15:0] Tx_pkt_length_rmon ;
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input Tx_apply_rmon ;
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input [2:0] Tx_pkt_err_type_rmon;
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//Tx_RMON
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input [2:0] Rx_pkt_type_rmon ;
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input [15:0] Rx_pkt_length_rmon ;
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input Rx_apply_rmon ;
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input [2:0] Rx_pkt_err_type_rmon;
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//CPU
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input [5:0] CPU_rd_addr ;
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input CPU_rd_apply ;
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output CPU_rd_grant ;
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output [31:0] CPU_rd_dout ;
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//******************************************************************************
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//interface signals
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//******************************************************************************
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wire Reg_apply_0 ;
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wire [4:0] Reg_addr_0 ;
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wire [15:0] Reg_data_0 ;
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wire Reg_next_0 ;
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wire Reg_apply_1 ;
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wire [4:0] Reg_addr_1 ;
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wire [15:0] Reg_data_1 ;
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wire Reg_next_1 ;
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wire [5:0] Addra ;
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wire [31:0] Dina ;
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wire [31:0] Douta ;
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wire Wea ;
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//******************************************************************************
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assign RxAddrb=0;
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assign TxAddrb=0;
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RMON_addr_gen U_0_Rx_RMON_addr_gen(
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.Clk (Clk ),
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.Reset (Reset ),
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//RMON (//RMON ),
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.Pkt_type_rmon (Rx_pkt_type_rmon ),
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.Pkt_length_rmon (Rx_pkt_length_rmon ),
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.Apply_rmon (Rx_apply_rmon ),
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.Pkt_err_type_rmon (Rx_pkt_err_type_rmon ),
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//Rmon_ctrl (//Rron_ctrl ),
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.Reg_apply (Reg_apply_0 ),
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.Reg_addr (Reg_addr_0 ),
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.Reg_data (Reg_data_0 ),
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.Reg_next (Reg_next_0 ),
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//CPU (//CPU ),
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.Reg_drop_apply ( ));
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RMON_addr_gen U_0_Tx_RMON_addr_gen(
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.Clk (Clk ),
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.Reset (Reset ),
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//RMON (//RMON ),
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.Pkt_type_rmon (Tx_pkt_type_rmon ),
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.Pkt_length_rmon (Tx_pkt_length_rmon ),
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.Apply_rmon (Tx_apply_rmon ),
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.Pkt_err_type_rmon (Tx_pkt_err_type_rmon ),
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//Rmon_ctrl (//Rron_ctrl ),
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.Reg_apply (Reg_apply_1 ),
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.Reg_addr (Reg_addr_1 ),
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.Reg_data (Reg_data_1 ),
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.Reg_next (Reg_next_1 ),
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//CPU (//CPU ),
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.Reg_drop_apply ( ));
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RMON_CTRL U_RMON_CTRL(
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.Clk (Clk ),
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.Reset (Reset ),
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//RMON_CTRL (//RMON_CTRL ),
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.Reg_apply_0 (Reg_apply_0 ),
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.Reg_addr_0 (Reg_addr_0 ),
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.Reg_data_0 (Reg_data_0 ),
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.Reg_next_0 (Reg_next_0 ),
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.Reg_apply_1 (Reg_apply_1 ),
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.Reg_addr_1 (Reg_addr_1 ),
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.Reg_data_1 (Reg_data_1 ),
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.Reg_next_1 (Reg_next_1 ),
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//dual-port ram (//dual-port ram ),
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.Addra (Addra ),
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.Dina (Dina ),
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.Douta (Douta ),
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.Wea (Wea ),
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//CPU (//CPU ),
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.CPU_rd_addr (CPU_rd_addr ),
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.CPU_rd_apply (CPU_rd_apply ),
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.CPU_rd_grant (CPU_rd_grant ),
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.CPU_rd_dout (CPU_rd_dout )
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);
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RMON_dpram U_Rx_RMON_dpram(
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.Reset (Reset ),
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.Clk (Clk ),
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//port-a for Rmon (//port-a for Rmon ),
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.Addra (Addra ),
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.Dina (Dina ),
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.Douta ( ),
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.Wea (Wea ),
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//port-b for CPU (//port-b for CPU ),
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.Addrb (Addra ),
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.Doutb (Douta ));
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endmodule
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