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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Blame information for rev 14

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//----------------------------------------------------------------------
// Srdy/Drdy FIFO Head "B"
//
// Building block for FIFOs.  The "B" (big) FIFO is design for larger FIFOs
// based around memories, with sizes that may not be a power of 2.  This
// FIFO has a limitation that at most (depth-1) entries may be used.
//
// The bound inputs allow multiple FIFO controllers to share a single
// memory.  The enable input is for arbitration between multiple FIFO
// controllers, or between the fifo head and tail controllers on a
// single port memory.
//
// The commit parameter enables write/commit behavior.  This creates
// two write pointers, one which is used for writing to memory and
// a commit pointer which is sent to the tail block.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_fifo_head_b
  #(parameter depth=16,
    parameter commit=0,
    parameter asz=$clog2(depth)
  )
  (
   input       clk,
   input       reset,
   input       enable,
   input       c_commit,
   input       c_abort,  // should be asserted when c_srdy == 0
   input       c_srdy,
   output      c_drdy,
 
   input [asz-1:0]  bound_low,
   input [asz-1:0]  bound_high,
 
   input [asz-1:0]      rdptr,
   output reg [asz-1:0] cur_wrptr,
   output reg [asz-1:0] com_wrptr,
   output reg         mem_we
   );
 
  reg [asz-1:0]       nxt_wrptr;
  reg [asz-1:0]       wrptr_p1;
  reg                   empty;
  reg                   full, nxt_full;
  reg [asz-1:0]         nxt_com_wrptr;
 
  assign                c_drdy = !nxt_full & enable;
 
  always @*
    begin
      if (cur_wrptr[asz-1:0] == bound_high)
        begin
          wrptr_p1[asz-1:0] = bound_low;
        end
      else
        wrptr_p1 = cur_wrptr + 1;
 
      //empty = (cur_wrptr == rdptr) & !full;
      empty = (cur_wrptr == rdptr);
 
      // special-case -- if we do abort on a full FIFO
      // force full flag to clear
/* -----\/----- EXCLUDED -----\/-----
      if ((commit == 1) && c_abort && full)
        nxt_full = 0;
      else
        nxt_full = ( (!full & (wrptr_p1 == rdptr)) | (full & (cur_wrptr == rdptr)));
 -----/\----- EXCLUDED -----/\----- */
      nxt_full = (wrptr_p1 == rdptr);
 
      if ((commit == 1) && c_abort)
        begin
          nxt_wrptr = com_wrptr;
        end
      else if (enable & c_srdy & !nxt_full)
        begin
          nxt_wrptr = wrptr_p1;
          mem_we = 1;
        end
      else
        begin
          nxt_wrptr = cur_wrptr;
          mem_we = 0;
        end
    end
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          cur_wrptr <= `SDLIB_DELAY bound_low;
          full  <= `SDLIB_DELAY 0;
        end
      else
        begin
          cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
          full  <= `SDLIB_DELAY nxt_full;
        end // else: !if(reset)
    end // always @ (posedge clk)
 
  generate
    if (commit)
      begin
        always @*
          begin
            if (enable & c_commit & !c_abort & c_srdy & !nxt_full)
              nxt_com_wrptr = wrptr_p1;
            else
              nxt_com_wrptr = com_wrptr;
          end
 
        always @(posedge clk)
          begin
            if (reset)
              com_wrptr <= `SDLIB_DELAY bound_low;
            else
              com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
          end
      end // if (commit)
    else
      begin
        always @*
          com_wrptr = cur_wrptr;
      end
  endgenerate
 
endmodule // fifo_head
 

Line No.	Rev	Author	Line
1	2	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy FIFO Head "B"`
3			`//`
4			`// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs`
5	14	ghutchis	`// based around memories, with sizes that may not be a power of 2. This`
6			`// FIFO has a limitation that at most (depth-1) entries may be used.`
7	2	ghutchis	`//`
8			`// The bound inputs allow multiple FIFO controllers to share a single`
9			`// memory. The enable input is for arbitration between multiple FIFO`
10			`// controllers, or between the fifo head and tail controllers on a`
11			`// single port memory.`
12			`//`
13			`// The commit parameter enables write/commit behavior. This creates`
14			`// two write pointers, one which is used for writing to memory and`
15			`// a commit pointer which is sent to the tail block.`
16			`//`
17			`// Naming convention: c = consumer, p = producer, i = internal interface`
18			`//----------------------------------------------------------------------`
19			`// Author: Guy Hutchison`
20			`//`
21			`// This block is uncopyrighted and released into the public domain.`
22			`//----------------------------------------------------------------------`
23
24			`// delay unit for nonblocking assigns, default is to #1`
25			`ifndef SDLIB_DELAY
26			`define SDLIB_DELAY #1
27			`endif
28
29			`module sd_fifo_head_b`
30			`#(parameter depth=16,`
31			`parameter commit=0,`
32			`parameter asz=$clog2(depth)`
33			`)`
34			`(`
35			`input clk,`
36			`input reset,`
37			`input enable,`
38			`input c_commit,`
39			`input c_abort, // should be asserted when c_srdy == 0`
40			`input c_srdy,`
41			`output c_drdy,`
42
43			`input [asz-1:0] bound_low,`
44			`input [asz-1:0] bound_high,`
45
46			`input [asz-1:0] rdptr,`
47			`output reg [asz-1:0] cur_wrptr,`
48			`output reg [asz-1:0] com_wrptr,`
49			`output reg mem_we`
50			`);`
51
52			`reg [asz-1:0] nxt_wrptr;`
53			`reg [asz-1:0] wrptr_p1;`
54			`reg empty;`
55			`reg full, nxt_full;`
56			`reg [asz-1:0] nxt_com_wrptr;`
57
58	14	ghutchis	`assign c_drdy = !nxt_full & enable;`
59	2	ghutchis
60			`always @*`
61			`begin`
62			`if (cur_wrptr[asz-1:0] == bound_high)`
63			`begin`
64			`wrptr_p1[asz-1:0] = bound_low;`
65			`end`
66			`else`
67			`wrptr_p1 = cur_wrptr + 1;`
68
69	14	ghutchis	`//empty = (cur_wrptr == rdptr) & !full;`
70			`empty = (cur_wrptr == rdptr);`
71	2	ghutchis
72	14	ghutchis	`// special-case -- if we do abort on a full FIFO`
73			`// force full flag to clear`
74			`/* -----\/----- EXCLUDED -----\/-----`
75			`if ((commit == 1) && c_abort && full)`
76			`nxt_full = 0;`
77			`else`
78			`nxt_full = ( (!full & (wrptr_p1 == rdptr)) \| (full & (cur_wrptr == rdptr)));`
79			`-----/\----- EXCLUDED -----/\----- */`
80			`nxt_full = (wrptr_p1 == rdptr);`
81
82	2	ghutchis	`if ((commit == 1) && c_abort)`
83			`begin`
84			`nxt_wrptr = com_wrptr;`
85			`end`
86	14	ghutchis	`else if (enable & c_srdy & !nxt_full)`
87	2	ghutchis	`begin`
88			`nxt_wrptr = wrptr_p1;`
89			`mem_we = 1;`
90			`end`
91			`else`
92			`begin`
93			`nxt_wrptr = cur_wrptr;`
94			`mem_we = 0;`
95			`end`
96			`end`
97
98			`always @(posedge clk)`
99			`begin`
100			`if (reset)`
101			`begin`
102			cur_wrptr <= `SDLIB_DELAY bound_low;
103			full <= `SDLIB_DELAY 0;
104			`end`
105			`else`
106			`begin`
107			cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
108			full <= `SDLIB_DELAY nxt_full;
109			`end // else: !if(reset)`
110			`end // always @ (posedge clk)`
111
112	6	ghutchis	`generate`
113			`if (commit)`
114	2	ghutchis	`begin`
115	6	ghutchis	`always @*`
116			`begin`
117	14	ghutchis	`if (enable & c_commit & !c_abort & c_srdy & !nxt_full)`
118	6	ghutchis	`nxt_com_wrptr = wrptr_p1;`
119			`else`
120			`nxt_com_wrptr = com_wrptr;`
121			`end`
122	2	ghutchis
123	6	ghutchis	`always @(posedge clk)`
124			`begin`
125			`if (reset)`
126			com_wrptr <= `SDLIB_DELAY bound_low;
127			`else`
128			com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
129			`end`
130			`end // if (commit)`
131			`else`
132	2	ghutchis	`begin`
133	6	ghutchis	`always @*`
134			`com_wrptr = cur_wrptr;`
135	2	ghutchis	`end`
136			`endgenerate`
137
138			`endmodule // fifo_head`
139

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Blame information for rev 14