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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Blame information for rev 16

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//----------------------------------------------------------------------
// Srdy/Drdy FIFO Head "B"
//
// Building block for FIFOs.  The "B" (big) FIFO is design for larger FIFOs
// based around memories, with sizes that may not be a power of 2.  This
// FIFO has a limitation that at most (depth-1) entries may be used.
//
// The bound inputs allow multiple FIFO controllers to share a single
// memory.  The enable input is for arbitration between multiple FIFO
// controllers, or between the fifo head and tail controllers on a
// single port memory.
//
// The commit parameter enables write/commit behavior.  This creates
// two write pointers, one which is used for writing to memory and
// a commit pointer which is sent to the tail block.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
// Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_fifo_head_b
  #(parameter depth=16,
    parameter commit=0,
    parameter asz=$clog2(depth),
    parameter usz=$clog2(depth+1)
  )
  (
   input       clk,
   input       reset,
   input       enable,
   input       c_commit,
   input       c_abort,  // should be asserted when c_srdy == 0
   input       c_srdy,
   output      c_drdy,
 
   input [asz-1:0]  bound_low,
   input [asz-1:0]  bound_high,
 
   input [asz-1:0]      rdptr,
   output reg [asz-1:0] cur_wrptr,
   output reg [asz-1:0] com_wrptr,
   output reg [usz-1:0] c_usage,
   output reg         mem_we
   );
 
  reg [asz-1:0]       nxt_wrptr;
  reg [asz-1:0]       wrptr_p1;
  reg                   empty;
  reg                   full, nxt_full;
  reg [asz-1:0]         nxt_com_wrptr;
  reg [usz:0]            tmp_usage;
  wire [usz-1:0]         fifo_size;
 
  assign fifo_size = bound_high - bound_low + 1;
 
  assign                c_drdy = !nxt_full & enable;
 
  always @*
    begin
      if (cur_wrptr[asz-1:0] == bound_high)
        begin
          wrptr_p1[asz-1:0] = bound_low;
        end
      else
        wrptr_p1 = cur_wrptr + 1;
 
      //empty = (cur_wrptr == rdptr) & !full;
      empty = (cur_wrptr == rdptr);
 
      // special-case -- if we do abort on a full FIFO
      // force full flag to clear
/* -----\/----- EXCLUDED -----\/-----
      if ((commit == 1) && c_abort && full)
        nxt_full = 0;
      else
        nxt_full = ( (!full & (wrptr_p1 == rdptr)) | (full & (cur_wrptr == rdptr)));
 -----/\----- EXCLUDED -----/\----- */
      nxt_full = (wrptr_p1 == rdptr);
 
      if ((commit == 1) && c_abort)
        begin
          nxt_wrptr = com_wrptr;
        end
      else if (enable & c_srdy & !nxt_full)
        begin
          nxt_wrptr = wrptr_p1;
          mem_we = 1;
        end
      else
        begin
          nxt_wrptr = cur_wrptr;
          mem_we = 0;
        end
 
      tmp_usage = cur_wrptr[asz-1:0] - rdptr[asz-1:0];
      if (~tmp_usage[usz])
        c_usage = tmp_usage[usz-1:0];
      else
        c_usage = fifo_size - (rdptr[asz-1:0] - cur_wrptr[asz-1:0]);
    end
 
  always @(posedge clk)
    begin
      if (reset)
        begin
          cur_wrptr <= `SDLIB_DELAY bound_low;
          full  <= `SDLIB_DELAY 0;
        end
      else
        begin
          cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
          full  <= `SDLIB_DELAY nxt_full;
        end // else: !if(reset)
    end // always @ (posedge clk)
 
  generate
    if (commit)
      begin
        always @*
          begin
            if (enable & c_commit & !c_abort & c_srdy & !nxt_full)
              nxt_com_wrptr = wrptr_p1;
            else
              nxt_com_wrptr = com_wrptr;
          end
 
        always @(posedge clk)
          begin
            if (reset)
              com_wrptr <= `SDLIB_DELAY bound_low;
            else
              com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
          end
      end // if (commit)
    else
      begin
        always @*
          com_wrptr = cur_wrptr;
      end
  endgenerate
 
endmodule // fifo_head
 

Line No.	Rev	Author	Line
1	2	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/Drdy FIFO Head "B"`
3			`//`
4			`// Building block for FIFOs. The "B" (big) FIFO is design for larger FIFOs`
5	14	ghutchis	`// based around memories, with sizes that may not be a power of 2. This`
6			`// FIFO has a limitation that at most (depth-1) entries may be used.`
7	2	ghutchis	`//`
8			`// The bound inputs allow multiple FIFO controllers to share a single`
9			`// memory. The enable input is for arbitration between multiple FIFO`
10			`// controllers, or between the fifo head and tail controllers on a`
11			`// single port memory.`
12			`//`
13			`// The commit parameter enables write/commit behavior. This creates`
14			`// two write pointers, one which is used for writing to memory and`
15			`// a commit pointer which is sent to the tail block.`
16			`//`
17			`// Naming convention: c = consumer, p = producer, i = internal interface`
18			`//----------------------------------------------------------------------`
19			`// Author: Guy Hutchison`
20			`//`
21			`// This block is uncopyrighted and released into the public domain.`
22			`//----------------------------------------------------------------------`
23
24			`// delay unit for nonblocking assigns, default is to #1`
25			`ifndef SDLIB_DELAY
26			`define SDLIB_DELAY #1
27			`endif
28
29			`module sd_fifo_head_b`
30			`#(parameter depth=16,`
31			`parameter commit=0,`
32	16	ghutchis	`parameter asz=$clog2(depth),`
33			`parameter usz=$clog2(depth+1)`
34	2	ghutchis	`)`
35			`(`
36			`input clk,`
37			`input reset,`
38			`input enable,`
39			`input c_commit,`
40			`input c_abort, // should be asserted when c_srdy == 0`
41			`input c_srdy,`
42			`output c_drdy,`
43
44			`input [asz-1:0] bound_low,`
45			`input [asz-1:0] bound_high,`
46
47			`input [asz-1:0] rdptr,`
48			`output reg [asz-1:0] cur_wrptr,`
49			`output reg [asz-1:0] com_wrptr,`
50	16	ghutchis	`output reg [usz-1:0] c_usage,`
51	2	ghutchis	`output reg mem_we`
52			`);`
53
54			`reg [asz-1:0] nxt_wrptr;`
55			`reg [asz-1:0] wrptr_p1;`
56			`reg empty;`
57			`reg full, nxt_full;`
58			`reg [asz-1:0] nxt_com_wrptr;`
59	16	ghutchis	`reg [usz:0] tmp_usage;`
60			`wire [usz-1:0] fifo_size;`
61	2	ghutchis
62	16	ghutchis	`assign fifo_size = bound_high - bound_low + 1;`
63
64	14	ghutchis	`assign c_drdy = !nxt_full & enable;`
65	2	ghutchis
66			`always @*`
67			`begin`
68			`if (cur_wrptr[asz-1:0] == bound_high)`
69			`begin`
70			`wrptr_p1[asz-1:0] = bound_low;`
71			`end`
72			`else`
73			`wrptr_p1 = cur_wrptr + 1;`
74
75	14	ghutchis	`//empty = (cur_wrptr == rdptr) & !full;`
76			`empty = (cur_wrptr == rdptr);`
77	2	ghutchis
78	14	ghutchis	`// special-case -- if we do abort on a full FIFO`
79			`// force full flag to clear`
80			`/* -----\/----- EXCLUDED -----\/-----`
81			`if ((commit == 1) && c_abort && full)`
82			`nxt_full = 0;`
83			`else`
84			`nxt_full = ( (!full & (wrptr_p1 == rdptr)) \| (full & (cur_wrptr == rdptr)));`
85			`-----/\----- EXCLUDED -----/\----- */`
86			`nxt_full = (wrptr_p1 == rdptr);`
87
88	2	ghutchis	`if ((commit == 1) && c_abort)`
89			`begin`
90			`nxt_wrptr = com_wrptr;`
91			`end`
92	14	ghutchis	`else if (enable & c_srdy & !nxt_full)`
93	2	ghutchis	`begin`
94			`nxt_wrptr = wrptr_p1;`
95			`mem_we = 1;`
96			`end`
97			`else`
98			`begin`
99			`nxt_wrptr = cur_wrptr;`
100			`mem_we = 0;`
101			`end`
102	16	ghutchis
103			`tmp_usage = cur_wrptr[asz-1:0] - rdptr[asz-1:0];`
104			`if (~tmp_usage[usz])`
105			`c_usage = tmp_usage[usz-1:0];`
106			`else`
107			`c_usage = fifo_size - (rdptr[asz-1:0] - cur_wrptr[asz-1:0]);`
108	2	ghutchis	`end`
109
110			`always @(posedge clk)`
111			`begin`
112			`if (reset)`
113			`begin`
114			cur_wrptr <= `SDLIB_DELAY bound_low;
115			full <= `SDLIB_DELAY 0;
116			`end`
117			`else`
118			`begin`
119			cur_wrptr <= `SDLIB_DELAY nxt_wrptr;
120			full <= `SDLIB_DELAY nxt_full;
121			`end // else: !if(reset)`
122			`end // always @ (posedge clk)`
123
124	6	ghutchis	`generate`
125			`if (commit)`
126	2	ghutchis	`begin`
127	6	ghutchis	`always @*`
128			`begin`
129	14	ghutchis	`if (enable & c_commit & !c_abort & c_srdy & !nxt_full)`
130	6	ghutchis	`nxt_com_wrptr = wrptr_p1;`
131			`else`
132			`nxt_com_wrptr = com_wrptr;`
133			`end`
134	2	ghutchis
135	6	ghutchis	`always @(posedge clk)`
136			`begin`
137			`if (reset)`
138			com_wrptr <= `SDLIB_DELAY bound_low;
139			`else`
140			com_wrptr <= `SDLIB_DELAY nxt_com_wrptr;
141			`end`
142			`end // if (commit)`
143			`else`
144	2	ghutchis	`begin`
145	6	ghutchis	`always @*`
146			`com_wrptr = cur_wrptr;`
147	2	ghutchis	`end`
148			`endgenerate`
149
150			`endmodule // fifo_head`
151

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [buffers/] [sd_fifo_head_b.v] - Blame information for rev 16