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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_ajoin2.v] - Blame information for rev 30

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//----------------------------------------------------------------------
//  Srdy/drdy assymetric join
//
//  Performs assymetric join of 2 inputs by concatination.  Efficiency
//  of 0.5.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
//  Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks.  Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
 `define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_ajoin2
  #(parameter c1_width=8,
    parameter c2_width=8)
  (
   input              clk,
   input              reset,
 
   input              c1_srdy,
   output             c1_drdy,
   input [c1_width-1:0] c1_data,
 
   input              c2_srdy,
   output             c2_drdy,
   input [c2_width-1:0] c2_data,
 
   output             p_srdy,
 
   input              p_drdy,
   output reg [c1_width+c2_width-1:0] p_data
   );
  reg [c1_width+c2_width-1:0]    nxt_p_data;
 
  reg [1:0]          in_drdy, nxt_in_drdy;
 
  assign             {c2_drdy,c1_drdy} = in_drdy;
 
  always @*
    begin
      nxt_p_data = p_data;
      nxt_in_drdy = in_drdy;
 
      if (in_drdy[0])
        begin
          if (c1_srdy)
            begin
              nxt_in_drdy[0] = 0;
              nxt_p_data[c1_width-1:0] = c1_data;
            end
        end
      else if (p_srdy & p_drdy)
        nxt_in_drdy[0] = 1;
 
      if (in_drdy[1])
        begin
          if (c2_srdy)
            begin
              nxt_in_drdy[1] = 0;
              nxt_p_data[c2_width+c1_width-1:c1_width] = c2_data;
            end
        end
      else if (p_srdy & p_drdy)
        nxt_in_drdy[1] = 1;
    end
 
  always @(`SDLIB_CLOCKING)
    begin
      if (reset)
        begin
          in_drdy  <= `SDLIB_DELAY 2'b11;
          p_data <= `SDLIB_DELAY 0;
        end
      else
        begin
          in_drdy  <= `SDLIB_DELAY nxt_in_drdy;
          p_data <= `SDLIB_DELAY nxt_p_data;
        end // else: !if(reset)
    end // always @ (posedge clk)
 
  assign p_srdy = & (~in_drdy);
 
endmodule // it_output

Line No.	Rev	Author	Line
1	18	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/drdy assymetric join`
3			`//`
4			`// Performs assymetric join of 2 inputs by concatination. Efficiency`
5			`// of 0.5.`
6			`//`
7			`// Naming convention: c = consumer, p = producer, i = internal interface`
8			`//----------------------------------------------------------------------`
9			`// Author: Guy Hutchison`
10			`//`
11			`// This block is uncopyrighted and released into the public domain.`
12			`//----------------------------------------------------------------------`
13
14			`// Clocking statement for synchronous blocks. Default is for`
15			`// posedge clocking and positive async reset`
16			`ifndef SDLIB_CLOCKING
17			`define SDLIB_CLOCKING posedge clk or posedge reset
18			`endif
19
20			`// delay unit for nonblocking assigns, default is to #1`
21			`ifndef SDLIB_DELAY
22			`define SDLIB_DELAY #1
23			`endif
24
25			`module sd_ajoin2`
26			`#(parameter c1_width=8,`
27			`parameter c2_width=8)`
28			`(`
29	30	ghutchis	`input clk,`
30	18	ghutchis	`input reset,`
31
32			`input c1_srdy,`
33			`output c1_drdy,`
34			`input [c1_width-1:0] c1_data,`
35
36			`input c2_srdy,`
37			`output c2_drdy,`
38			`input [c2_width-1:0] c2_data,`
39
40			`output p_srdy,`
41
42			`input p_drdy,`
43			`output reg [c1_width+c2_width-1:0] p_data`
44			`);`
45			`reg [c1_width+c2_width-1:0] nxt_p_data;`
46
47			`reg [1:0] in_drdy, nxt_in_drdy;`
48
49			`assign {c2_drdy,c1_drdy} = in_drdy;`
50
51			`always @*`
52			`begin`
53			`nxt_p_data = p_data;`
54			`nxt_in_drdy = in_drdy;`
55
56			`if (in_drdy[0])`
57			`begin`
58			`if (c1_srdy)`
59			`begin`
60			`nxt_in_drdy[0] = 0;`
61			`nxt_p_data[c1_width-1:0] = c1_data;`
62			`end`
63			`end`
64			`else if (p_srdy & p_drdy)`
65			`nxt_in_drdy[0] = 1;`
66
67			`if (in_drdy[1])`
68			`begin`
69			`if (c2_srdy)`
70			`begin`
71			`nxt_in_drdy[1] = 0;`
72			`nxt_p_data[c2_width+c1_width-1:c1_width] = c2_data;`
73			`end`
74			`end`
75			`else if (p_srdy & p_drdy)`
76			`nxt_in_drdy[1] = 1;`
77			`end`
78
79			always @(`SDLIB_CLOCKING)
80			`begin`
81			`if (reset)`
82			`begin`
83			in_drdy <= `SDLIB_DELAY 2'b11;
84			p_data <= `SDLIB_DELAY 0;
85			`end`
86			`else`
87			`begin`
88			in_drdy <= `SDLIB_DELAY nxt_in_drdy;
89			p_data <= `SDLIB_DELAY nxt_p_data;
90			`end // else: !if(reset)`
91			`end // always @ (posedge clk)`
92
93			`assign p_srdy = & (~in_drdy);`
94
95			`endmodule // it_output`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_ajoin2.v] - Blame information for rev 30