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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_mirror.v] - Blame information for rev 14

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//----------------------------------------------------------------------
//  Srdy/drdy mirrored fork
//
//  Used when a single item of data needs to be used by more than one
//  block, and all blocks may finish at different times.  This creates
//  separate srdy/drdy signals for each block, and holds drdy to the
//  sender until all blocks have individually asserted drdy.
//
//  The input c_dst_vld allows the data to be selectively sent to some
//  or all of the downstream endpoints.  At least one bit in c_dst_vld
//  must be asserted with c_srdy.  If this functionality is not desired
//  the input should be tied to 0.
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
//  Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks.  Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
 `define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_mirror
  #(parameter mirror=2,
    parameter width=128)
  (input        clk,
   input        reset,
 
   input              c_srdy,
   //output reg         c_drdy,
   output             c_drdy,
   input [width-1:0]  c_data,
   input [mirror-1:0] c_dst_vld,
 
   output reg [mirror-1:0] p_srdy,
   input [mirror-1:0]      p_drdy,
   output reg [width-1:0]  p_data
   );
 
  reg                    state, nxt_state;
  reg [mirror-1:0]        nxt_p_srdy;
  reg                    load;
 
  always @(posedge clk)
    if (load)
      p_data <= `SDLIB_DELAY c_data;
 
  assign c_drdy = (p_srdy == 0);
 
  always @*
    begin
      nxt_p_srdy = p_srdy;
      load         = 0;
 
      if (p_srdy == {mirror{1'b0}})
          begin
            if (c_srdy)
              begin
                if (c_dst_vld == {mirror{1'b0}})
                  nxt_p_srdy = {mirror{1'b1}};
                else
                  nxt_p_srdy = c_dst_vld;
                load         = 1;
              end
          end
      else
        begin
          nxt_p_srdy = p_srdy & ~p_drdy;
        end
    end
 
  always @(`SDLIB_CLOCKING)
    begin
      if (reset)
        begin
          p_srdy   <= `SDLIB_DELAY {mirror{1'b0}};
          state    <= `SDLIB_DELAY 1'b0;
        end
      else
        begin
          p_srdy   <= `SDLIB_DELAY nxt_p_srdy;
          state    <= `SDLIB_DELAY nxt_state;
        end
    end
 
endmodule // sd_mirror

Line No.	Rev	Author	Line
1	2	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/drdy mirrored fork`
3			`//`
4			`// Used when a single item of data needs to be used by more than one`
5			`// block, and all blocks may finish at different times. This creates`
6			`// separate srdy/drdy signals for each block, and holds drdy to the`
7			`// sender until all blocks have individually asserted drdy.`
8			`//`
9			`// The input c_dst_vld allows the data to be selectively sent to some`
10			`// or all of the downstream endpoints. At least one bit in c_dst_vld`
11			`// must be asserted with c_srdy. If this functionality is not desired`
12			`// the input should be tied to 0.`
13			`//`
14			`// Naming convention: c = consumer, p = producer, i = internal interface`
15			`//----------------------------------------------------------------------`
16			`// Author: Guy Hutchison`
17			`//`
18			`// This block is uncopyrighted and released into the public domain.`
19			`//----------------------------------------------------------------------`
20
21			`// Clocking statement for synchronous blocks. Default is for`
22			`// posedge clocking and positive async reset`
23			`ifndef SDLIB_CLOCKING
24			`define SDLIB_CLOCKING posedge clk or posedge reset
25			`endif
26
27			`// delay unit for nonblocking assigns, default is to #1`
28			`ifndef SDLIB_DELAY
29			`define SDLIB_DELAY #1
30			`endif
31
32			`module sd_mirror`
33			`#(parameter mirror=2,`
34			`parameter width=128)`
35			`(input clk,`
36			`input reset,`
37
38			`input c_srdy,`
39	14	ghutchis	`//output reg c_drdy,`
40			`output c_drdy,`
41	2	ghutchis	`input [width-1:0] c_data,`
42			`input [mirror-1:0] c_dst_vld,`
43
44			`output reg [mirror-1:0] p_srdy,`
45			`input [mirror-1:0] p_drdy,`
46			`output reg [width-1:0] p_data`
47			`);`
48
49			`reg state, nxt_state;`
50			`reg [mirror-1:0] nxt_p_srdy;`
51			`reg load;`
52
53			`always @(posedge clk)`
54			`if (load)`
55			p_data <= `SDLIB_DELAY c_data;
56	14	ghutchis
57			`assign c_drdy = (p_srdy == 0);`
58
59	2	ghutchis	`always @*`
60			`begin`
61			`nxt_p_srdy = p_srdy;`
62			`load = 0;`
63
64	14	ghutchis	`if (p_srdy == {mirror{1'b0}})`
65	2	ghutchis	`begin`
66			`if (c_srdy)`
67			`begin`
68			`if (c_dst_vld == {mirror{1'b0}})`
69			`nxt_p_srdy = {mirror{1'b1}};`
70			`else`
71			`nxt_p_srdy = c_dst_vld;`
72			`load = 1;`
73			`end`
74			`end`
75	14	ghutchis	`else`
76			`begin`
77			`nxt_p_srdy = p_srdy & ~p_drdy;`
78			`end`
79	2	ghutchis	`end`
80
81			always @(`SDLIB_CLOCKING)
82			`begin`
83			`if (reset)`
84			`begin`
85			p_srdy <= `SDLIB_DELAY {mirror{1'b0}};
86			state <= `SDLIB_DELAY 1'b0;
87			`end`
88			`else`
89			`begin`
90			p_srdy <= `SDLIB_DELAY nxt_p_srdy;
91			state <= `SDLIB_DELAY nxt_state;
92			`end`
93			`end`
94
95			`endmodule // sd_mirror`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_mirror.v] - Blame information for rev 14