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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_rrmux.v] - Blame information for rev 24

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1 7 ghutchis
//----------------------------------------------------------------------
2 20 ghutchis
// Srdy/drdy round-robin arbiter
3 7 ghutchis
//
4 20 ghutchis
// Asserts drdy for an input and then moves to the next input.
5 7 ghutchis
//
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// This component supports multiple round-robin modes:
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//
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// Mode 0 : Each input gets a single cycle, regardless of data
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//          availability.  This mode functions like a TDM
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//          demultiplexer.  Output flow control will cause the
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//          component to stall, so that inputs do not miss their
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//          turn due to flow control.
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// Mode 1 : Each input can transmit for as long as it has data.
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//          When input deasserts, device will begin to hunt for a
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//          new input with data.
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// Mode 2 : Continue to accept input until the incoming data
17 24 ghutchis
//          matches a particular "end pattern".  The end pattern
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//          is provided on the c_rearb (re-arbitrate) input.  When
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//          c_rearb is high, will hunt for new inputs on next clock.
20 7 ghutchis
//
21 20 ghutchis
// This component also supports two arbitration modes: slow and fast.
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// slow rotates the grant from requestor to requestor cycle by cycle,
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// so each requestor gets serviced at most once every #inputs cycles.
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// This can be useful for producing a TDM-type interface, however
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// requestors may be delayed waiting for the grant to come around even
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// if there are no other requestors.
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//
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// Fast mode immediately grants the highest-priority requestor, however
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// it is drdy-noncompliant (drdy will not be asserted until srdy is
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// asserted).
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//
32 7 ghutchis
// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//  Author: Guy Hutchison
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//
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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// Clocking statement for synchronous blocks.  Default is for
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// posedge clocking and positive async reset
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`ifndef SDLIB_CLOCKING
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 `define SDLIB_CLOCKING posedge clk or posedge reset
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`endif
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// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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 `define SDLIB_DELAY #1
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`endif
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50 20 ghutchis
module sd_rrmux
51 7 ghutchis
  #(parameter width=8,
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    parameter inputs=2,
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    parameter mode=0,
54 20 ghutchis
    parameter fast_arb=0)
55 7 ghutchis
  (
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   input               clk,
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   input               reset,
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   input [(width*inputs)-1:0] c_data,
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   input [inputs-1:0]      c_srdy,
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   output  [inputs-1:0]    c_drdy,
62 24 ghutchis
   input                   c_rearb,  // for use with mode 2 only
63 7 ghutchis
 
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   output reg [width-1:0]  p_data,
65 18 ghutchis
   output [inputs-1:0]     p_grant,
66 7 ghutchis
   output reg              p_srdy,
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   input                   p_drdy
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   );
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  reg [inputs-1:0]    rr_state;
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  reg [inputs-1:0]    nxt_rr_state;
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  reg [$clog2(inputs)-1:0] data_ind;
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  wire [width-1:0]     rr_mux_grid [0:inputs-1];
76 10 ghutchis
  reg                  rr_locked;
77 7 ghutchis
  genvar               i;
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  integer              j;
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  assign c_drdy = rr_state & {inputs{p_drdy}};
81 18 ghutchis
  assign p_grant = rr_state;
82 20 ghutchis
 
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  function [inputs-1:0] nxt_grant;
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    input [inputs-1:0] cur_grant;
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    input [inputs-1:0] cur_req;
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    reg [inputs-1:0]   msk_req;
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    reg [inputs-1:0]   tmp_grant;
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    begin
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      msk_req = cur_req & ~((cur_grant - 1) | cur_grant);
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      tmp_grant = msk_req & (~msk_req + 1);
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      if (msk_req != 0)
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        nxt_grant = tmp_grant;
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      else
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        nxt_grant = cur_req & (~cur_req + 1);
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    end
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  endfunction
98 7 ghutchis
 
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  generate
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    for (i=0; i<inputs; i=i+1)
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      begin : grid_assign
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        assign rr_mux_grid[i] = c_data >> (i*width);
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      end
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    if (mode == 2)
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      begin : tp_gen
107 10 ghutchis
        reg nxt_rr_locked;
108 7 ghutchis
 
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        always @*
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          begin
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            data_ind = 0;
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            for (j=0; j<inputs; j=j+1)
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              if (rr_state[j])
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                data_ind = j;
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            nxt_rr_locked = rr_locked;
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            if ((c_srdy & rr_state) & (!rr_locked))
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              nxt_rr_locked = 1;
120 24 ghutchis
            else if ((c_srdy & rr_state & c_rearb) & p_drdy )
121 7 ghutchis
              nxt_rr_locked = 0;
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          end
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        always @(`SDLIB_CLOCKING)
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          begin
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            if (reset)
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              rr_locked <= `SDLIB_DELAY 0;
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            else
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              rr_locked <= `SDLIB_DELAY nxt_rr_locked;
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          end
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      end // block: tp_gen
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  endgenerate
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  always @*
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    begin
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      p_data = 0;
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      p_srdy = 0;
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      for (j=0; j<inputs; j=j+1)
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        if (rr_state[j])
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          begin
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            p_data = rr_mux_grid[j];
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            p_srdy = c_srdy[j];
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          end
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    end
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  always @*
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    begin
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      if ((mode ==  1) & (c_srdy & rr_state))
149
        nxt_rr_state = rr_state;
150
      else if ((mode == 0) & !p_drdy)
151
        nxt_rr_state = rr_state;
152 10 ghutchis
      else if ((mode == 2) & (rr_locked | (c_srdy & rr_state)))
153 7 ghutchis
        nxt_rr_state = rr_state;
154 20 ghutchis
      else if (fast_arb)
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        nxt_rr_state = nxt_grant (rr_state, c_srdy);
156 7 ghutchis
      else
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        nxt_rr_state = { rr_state[0], rr_state[inputs-1:1] };
158
    end
159
 
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  always @(`SDLIB_CLOCKING)
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    begin
162
      if (reset)
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        rr_state <= `SDLIB_DELAY 1;
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      else
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        rr_state <= `SDLIB_DELAY nxt_rr_state;
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    end
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168
endmodule // sd_rrmux

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