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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks/] [sd_rrmux.v] - Blame information for rev 30

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1 7 ghutchis
//----------------------------------------------------------------------
2 20 ghutchis
// Srdy/drdy round-robin arbiter
3 7 ghutchis
//
4 20 ghutchis
// Asserts drdy for an input and then moves to the next input.
5 7 ghutchis
//
6
// This component supports multiple round-robin modes:
7
//
8
// Mode 0 : Each input gets a single cycle, regardless of data
9
//          availability.  This mode functions like a TDM
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//          demultiplexer.  Output flow control will cause the
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//          component to stall, so that inputs do not miss their
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//          turn due to flow control.
13 30 ghutchis
// Mode 0 fast arb : Each input gets a single grant. If the
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//          output is not ready (p_drdy deasserted), then the
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//          machine will hold on that particular input until it
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//          receives a grant.  Once a single token has been
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//          accepted the machine will round-robin arbitrate.
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//          When there are no requests the machine returns to
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//          its default state.
20 7 ghutchis
// Mode 1 : Each input can transmit for as long as it has data.
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//          When input deasserts, device will begin to hunt for a
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//          new input with data.
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// Mode 2 : Continue to accept input until the incoming data
24 24 ghutchis
//          matches a particular "end pattern".  The end pattern
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//          is provided on the c_rearb (re-arbitrate) input.  When
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//          c_rearb is high, will hunt for new inputs on next clock.
27 7 ghutchis
//
28 20 ghutchis
// This component also supports two arbitration modes: slow and fast.
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// slow rotates the grant from requestor to requestor cycle by cycle,
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// so each requestor gets serviced at most once every #inputs cycles.
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// This can be useful for producing a TDM-type interface, however
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// requestors may be delayed waiting for the grant to come around even
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// if there are no other requestors.
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//
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// Fast mode immediately grants the highest-priority requestor, however
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// it is drdy-noncompliant (drdy will not be asserted until srdy is
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// asserted).
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//
39 7 ghutchis
// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//  Author: Guy Hutchison
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//
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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// Clocking statement for synchronous blocks.  Default is for
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// posedge clocking and positive async reset
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`ifndef SDLIB_CLOCKING
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 `define SDLIB_CLOCKING posedge clk or posedge reset
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`endif
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52
// delay unit for nonblocking assigns, default is to #1
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`ifndef SDLIB_DELAY
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 `define SDLIB_DELAY #1
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`endif
56
 
57 20 ghutchis
module sd_rrmux
58 7 ghutchis
  #(parameter width=8,
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    parameter inputs=2,
60 29 ghutchis
    parameter inputs_asz=1,  // log2(inputs)
61 7 ghutchis
    parameter mode=0,
62 20 ghutchis
    parameter fast_arb=0)
63 7 ghutchis
  (
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   input               clk,
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   input               reset,
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   input [(width*inputs)-1:0] c_data,
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   input [inputs-1:0]      c_srdy,
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   output  [inputs-1:0]    c_drdy,
70 24 ghutchis
   input                   c_rearb,  // for use with mode 2 only
71 7 ghutchis
 
72 30 ghutchis
   output     [width-1:0]  p_data,
73 18 ghutchis
   output [inputs-1:0]     p_grant,
74 30 ghutchis
   output                  p_srdy,
75 7 ghutchis
   input                   p_drdy
76
   );
77
 
78
  reg [inputs-1:0]    rr_state;
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  reg [inputs-1:0]    nxt_rr_state;
80
 
81 30 ghutchis
  //wire [width-1:0]     rr_mux_grid [0:inputs-1];
82 10 ghutchis
  reg                  rr_locked;
83 30 ghutchis
  //genvar               i;
84 7 ghutchis
  integer              j;
85
 
86
  assign c_drdy = rr_state & {inputs{p_drdy}};
87 18 ghutchis
  assign p_grant = rr_state;
88 20 ghutchis
 
89
  function [inputs-1:0] nxt_grant;
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    input [inputs-1:0] cur_grant;
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    input [inputs-1:0] cur_req;
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    reg [inputs-1:0]   msk_req;
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    reg [inputs-1:0]   tmp_grant;
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    begin
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      msk_req = cur_req & ~((cur_grant - 1) | cur_grant);
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      tmp_grant = msk_req & (~msk_req + 1);
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      if (msk_req != 0)
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        nxt_grant = tmp_grant;
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      else
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        nxt_grant = cur_req & (~cur_req + 1);
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    end
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  endfunction
104 7 ghutchis
 
105 30 ghutchis
  always @*
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    begin
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      data_ind = 0;
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      for (j=0; j<inputs; j=j+1)
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        if (rr_state[j])
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          data_ind = j;
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    end
112
 
113 7 ghutchis
  generate
114 30 ghutchis
/* -----\/----- EXCLUDED -----\/-----
115 7 ghutchis
    for (i=0; i<inputs; i=i+1)
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      begin : grid_assign
117 30 ghutchis
        wire [width-1:0] temp;
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        assign temp = c_data >> (i*width);
119 7 ghutchis
        assign rr_mux_grid[i] = c_data >> (i*width);
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      end
121 30 ghutchis
 -----/\----- EXCLUDED -----/\----- */
122 7 ghutchis
 
123
    if (mode == 2)
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      begin : tp_gen
125 10 ghutchis
        reg nxt_rr_locked;
126 29 ghutchis
        reg selected_srdy;
127 7 ghutchis
 
128
        always @*
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          begin
130 30 ghutchis
/* -----\/----- EXCLUDED -----\/-----
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            data_ind = 0;
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            for (j=0; j<inputs; j=j+1)
133
              if (rr_state[j])
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                data_ind = j;
135
 -----/\----- EXCLUDED -----/\----- */
136
 
137
            nxt_rr_locked = rr_locked;
138
 
139
            if ((c_srdy & rr_state) & (!rr_locked))
140
              nxt_rr_locked = 1;
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            else if ((c_srdy & rr_state & c_rearb) & p_drdy )
142 29 ghutchis
              nxt_rr_locked = 0;
143
            else if ((nxt_rr_state != rr_state) && (nxt_rr_state != 0))
144 7 ghutchis
              nxt_rr_locked = 1;
145 29 ghutchis
            else
146
              nxt_rr_locked = rr_locked;
147 7 ghutchis
          end
148
 
149
        always @(`SDLIB_CLOCKING)
150
          begin
151
            if (reset)
152
              rr_locked <= `SDLIB_DELAY 0;
153
            else
154
              rr_locked <= `SDLIB_DELAY nxt_rr_locked;
155
          end
156
      end // block: tp_gen
157
  endgenerate
158
 
159 30 ghutchis
  assign p_srdy = |(rr_state & c_srdy);
160
  assign p_data = c_data[data_ind*width +: width];
161 7 ghutchis
 
162
  always @*
163
    begin
164
      if ((mode ==  1) & (c_srdy & rr_state))
165
        nxt_rr_state = rr_state;
166 30 ghutchis
      else if ((mode == 0) && !p_drdy && !fast_arb)
167 7 ghutchis
        nxt_rr_state = rr_state;
168 30 ghutchis
      else if ((mode == 0) && |(rr_state & c_srdy) && !p_drdy && fast_arb)
169
        nxt_rr_state = rr_state;
170 10 ghutchis
      else if ((mode == 2) & (rr_locked | (c_srdy & rr_state)))
171 7 ghutchis
        nxt_rr_state = rr_state;
172 20 ghutchis
      else if (fast_arb)
173
        nxt_rr_state = nxt_grant (rr_state, c_srdy);
174 7 ghutchis
      else
175
        nxt_rr_state = { rr_state[0], rr_state[inputs-1:1] };
176
    end
177
 
178
  always @(`SDLIB_CLOCKING)
179
    begin
180
      if (reset)
181 30 ghutchis
        rr_state <= `SDLIB_DELAY (fast_arb)? 0 : 1;
182 7 ghutchis
      else
183
        rr_state <= `SDLIB_DELAY nxt_rr_state;
184
    end
185
 
186
endmodule // sd_rrmux

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