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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_bpdrop.v] - Blame information for rev 26

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//----------------------------------------------------------------------
// Srdy/drdy backpressure drop (control path only)
//
// Monitors the srdy/drdy signals and looks for backpressure on the
// consumer interface which exceeds a certain time (in clocks).  If
// the time threshold is exceeded, sinks the packet until the end
// of a token frame.
//
// Naming convention: c = consumer, p = producer, 
// n = non-timing closed (combintorial) output
//----------------------------------------------------------------------
//  Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks.  Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
 `define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_bpdrop
  #(parameter cnt_sz = 3)
  (
   input               clk,
   input               reset,
 
   input [cnt_sz-1:0]  g_max_count,
 
   input               c_srdy,
   input               c_fr_start, // start of frame signal
   input               c_fr_end,   // end of frame signal
   output reg          nc_drdy,
 
   output reg          np_srdy,
   input               p_drdy
   );
 
  localparam s_idle = 2'b00, s_xfer = 2'b01, s_sink = 2'b11;
 
  reg [1:0]            state, nxt_state;
  reg [cnt_sz-1:0]     count, nxt_count;
 
  always @*
    begin
      nc_drdy = 0;
      np_srdy = 0;
      nxt_state = state;
      nxt_count = count;
 
      case (state)
        s_idle :
          begin
 
            if (c_srdy & c_fr_start)
              begin
                if (p_drdy)
                  begin
                    nc_drdy = 1;
                    np_srdy = 1;
                    nxt_state = s_xfer;
                  end
                else
                  begin
                    nxt_count = count + 1;
                    if (count >= g_max_count)
                      begin
                        nc_drdy = 1;
                        nxt_state = s_sink;
                      end
                  end
              end
            else
              begin
                nxt_count = 0;
 
                // if data other than c_fr_start shows up sink it
                if (c_srdy)
                  nc_drdy = 1;
              end
          end // case: s_idle
 
        s_xfer :
          begin
            nxt_count = 0;
            if (c_srdy & p_drdy)
              begin
                nc_drdy = 1;
                np_srdy = 1;
                if (c_fr_end)
                  nxt_state = s_idle;
              end
          end // case: s_xfer
 
        s_sink :
          begin
            nc_drdy = 1;
            nxt_count = 0;
 
            if (c_srdy & c_fr_end)
              nxt_state = s_idle;
          end
 
        default : nxt_state = s_idle;
      endcase // case (state)
    end // always @ *
 
  always @(`SDLIB_CLOCKING)
    begin
      if (reset)
        begin
          state <= `SDLIB_DELAY s_idle;
          count <= `SDLIB_DELAY 0;
        end
      else
        begin
          state <= `SDLIB_DELAY nxt_state;
          count <= `SDLIB_DELAY nxt_count;
        end
    end // always @ (`SDLIB_CLOCKING)
 
 
endmodule // sd_rrmux

Line No.	Rev	Author	Line
1	26	ghutchis	`//----------------------------------------------------------------------`
2			`// Srdy/drdy backpressure drop (control path only)`
3			`//`
4			`// Monitors the srdy/drdy signals and looks for backpressure on the`
5			`// consumer interface which exceeds a certain time (in clocks). If`
6			`// the time threshold is exceeded, sinks the packet until the end`
7			`// of a token frame.`
8			`//`
9			`// Naming convention: c = consumer, p = producer,`
10			`// n = non-timing closed (combintorial) output`
11			`//----------------------------------------------------------------------`
12			`// Author: Guy Hutchison`
13			`//`
14			`// This block is uncopyrighted and released into the public domain.`
15			`//----------------------------------------------------------------------`
16
17			`// Clocking statement for synchronous blocks. Default is for`
18			`// posedge clocking and positive async reset`
19			`ifndef SDLIB_CLOCKING
20			`define SDLIB_CLOCKING posedge clk or posedge reset
21			`endif
22
23			`// delay unit for nonblocking assigns, default is to #1`
24			`ifndef SDLIB_DELAY
25			`define SDLIB_DELAY #1
26			`endif
27
28			`module sd_bpdrop`
29			`#(parameter cnt_sz = 3)`
30			`(`
31			`input clk,`
32			`input reset,`
33
34			`input [cnt_sz-1:0] g_max_count,`
35
36			`input c_srdy,`
37			`input c_fr_start, // start of frame signal`
38			`input c_fr_end, // end of frame signal`
39			`output reg nc_drdy,`
40
41			`output reg np_srdy,`
42			`input p_drdy`
43			`);`
44
45			`localparam s_idle = 2'b00, s_xfer = 2'b01, s_sink = 2'b11;`
46
47			`reg [1:0] state, nxt_state;`
48			`reg [cnt_sz-1:0] count, nxt_count;`
49
50			`always @*`
51			`begin`
52			`nc_drdy = 0;`
53			`np_srdy = 0;`
54			`nxt_state = state;`
55			`nxt_count = count;`
56
57			`case (state)`
58			`s_idle :`
59			`begin`
60
61			`if (c_srdy & c_fr_start)`
62			`begin`
63			`if (p_drdy)`
64			`begin`
65			`nc_drdy = 1;`
66			`np_srdy = 1;`
67			`nxt_state = s_xfer;`
68			`end`
69			`else`
70			`begin`
71			`nxt_count = count + 1;`
72			`if (count >= g_max_count)`
73			`begin`
74			`nc_drdy = 1;`
75			`nxt_state = s_sink;`
76			`end`
77			`end`
78			`end`
79			`else`
80			`begin`
81			`nxt_count = 0;`
82
83			`// if data other than c_fr_start shows up sink it`
84			`if (c_srdy)`
85			`nc_drdy = 1;`
86			`end`
87			`end // case: s_idle`
88
89			`s_xfer :`
90			`begin`
91			`nxt_count = 0;`
92			`if (c_srdy & p_drdy)`
93			`begin`
94			`nc_drdy = 1;`
95			`np_srdy = 1;`
96			`if (c_fr_end)`
97			`nxt_state = s_idle;`
98			`end`
99			`end // case: s_xfer`
100
101			`s_sink :`
102			`begin`
103			`nc_drdy = 1;`
104			`nxt_count = 0;`
105
106			`if (c_srdy & c_fr_end)`
107			`nxt_state = s_idle;`
108			`end`
109
110			`default : nxt_state = s_idle;`
111			`endcase // case (state)`
112			`end // always @ *`
113
114			always @(`SDLIB_CLOCKING)
115			`begin`
116			`if (reset)`
117			`begin`
118			state <= `SDLIB_DELAY s_idle;
119			count <= `SDLIB_DELAY 0;
120			`end`
121			`else`
122			`begin`
123			state <= `SDLIB_DELAY nxt_state;
124			count <= `SDLIB_DELAY nxt_count;
125			`end`
126			end // always @ (`SDLIB_CLOCKING)
127
128
129			`endmodule // sd_rrmux`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_bpdrop.v] - Blame information for rev 26