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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_scoreboard.v] - Blame information for rev 18

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1 18 ghutchis
//----------------------------------------------------------------------
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//  Scoreboard
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//
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// Keeps track of data regarding N items.  Allows multiple entities
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// to track data about a particular item.  Supports masked writes,
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// allowing only part of a record to be updated by a particular
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// transaction.
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//
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// Naming convention: c = consumer, p = producer, i = internal interface
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//----------------------------------------------------------------------
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//  Author: Guy Hutchison
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//
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// This block is uncopyrighted and released into the public domain.
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//----------------------------------------------------------------------
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module sd_scoreboard
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  #(parameter width=8,
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    parameter items=64,
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    parameter use_txid=0,
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    parameter use_mask=0,
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    parameter txid_sz=2,
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    parameter asz=$clog2(items))
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  (input      clk,
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   input      reset,
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   input      c_srdy,
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   output     c_drdy,
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   input      c_req_type, // 0=read, 1=write
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   input [txid_sz-1:0] c_txid,
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   input [width-1:0] c_mask,
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   input [width-1:0] c_data,
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   input [asz-1:0]   c_itemid,
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   output     p_srdy,
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   input      p_drdy,
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   output [txid_sz-1:0] p_txid,
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   output [width-1:0]   p_data
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   );
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  localparam tot_in_sz = width*2+txid_sz+asz+1;
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  wire                  ip_req_type; // 0=read, 1=write
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  wire [txid_sz-1:0]    ip_txid;
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  wire [width-1:0]      ip_mask;
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  wire [width-1:0]      ip_data;
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  wire [asz-1:0]        ip_itemid;
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  wire [txid_sz-1:0]    ic_txid;
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  wire [width-1:0]      ic_data;
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  /*AUTOWIRE*/
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  // Beginning of automatic wires (for undeclared instantiated-module outputs)
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  wire [asz-1:0]        addr;                   // From fsm of sd_scoreboard_fsm.v
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  wire [width-1:0]      d_in;                   // From fsm of sd_scoreboard_fsm.v
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  wire [width-1:0]      d_out;                  // From sb_mem of behave1p_mem.v
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  wire                  ic_drdy;                // From outhold of sd_output.v
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  wire                  ic_srdy;                // From fsm of sd_scoreboard_fsm.v
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  wire                  ip_drdy;                // From fsm of sd_scoreboard_fsm.v
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  wire                  ip_srdy;                // From inhold of sd_input.v
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  wire                  rd_en;                  // From fsm of sd_scoreboard_fsm.v
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  wire                  wr_en;                  // From fsm of sd_scoreboard_fsm.v
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  // End of automatics
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  sd_input #(.width(tot_in_sz)) inhold
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    (
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     .c_data     ({c_txid,c_req_type,c_itemid,c_mask,c_data}),
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     .ip_data    ({ip_txid,ip_req_type,ip_itemid,ip_mask,ip_data}),
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     /*AUTOINST*/
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     // Outputs
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     .c_drdy                            (c_drdy),
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     .ip_srdy                           (ip_srdy),
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     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .c_srdy                            (c_srdy),
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     .ip_drdy                           (ip_drdy));
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  behave1p_mem #(.depth(items), .width(width)) sb_mem
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    (
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     .addr                              (addr[asz-1:0]),
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     /*AUTOINST*/
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     // Outputs
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     .d_out                             (d_out[width-1:0]),
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     // Inputs
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     .wr_en                             (wr_en),
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     .rd_en                             (rd_en),
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     .clk                               (clk),
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     .d_in                              (d_in[width-1:0]));
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  sd_scoreboard_fsm #(width,items,use_txid,use_mask,txid_sz) fsm
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    (/*AUTOINST*/
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     // Outputs
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     .ip_drdy                           (ip_drdy),
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     .ic_srdy                           (ic_srdy),
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     .ic_txid                           (ic_txid[txid_sz-1:0]),
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     .ic_data                           (ic_data[width-1:0]),
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     .wr_en                             (wr_en),
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     .rd_en                             (rd_en),
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     .d_in                              (d_in[width-1:0]),
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     .addr                              (addr[asz-1:0]),
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     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .ip_srdy                           (ip_srdy),
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     .ip_req_type                       (ip_req_type),
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     .ip_txid                           (ip_txid[txid_sz-1:0]),
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     .ip_mask                           (ip_mask[width-1:0]),
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     .ip_data                           (ip_data[width-1:0]),
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     .ip_itemid                         (ip_itemid[asz-1:0]),
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     .ic_drdy                           (ic_drdy),
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     .d_out                             (d_out[width-1:0]));
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  sd_output #(.width(width+txid_sz)) outhold
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    (
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     .p_data                            ({p_txid,p_data}),
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     .ic_data                           ({ic_txid,ic_data}),
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     /*AUTOINST*/
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     // Outputs
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     .ic_drdy                           (ic_drdy),
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     .p_srdy                            (p_srdy),
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     // Inputs
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     .clk                               (clk),
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     .reset                             (reset),
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     .ic_srdy                           (ic_srdy),
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     .p_drdy                            (p_drdy));
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endmodule // sd_scoreboard
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// Local Variables:
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// verilog-library-directories:("." "../closure" "../memory")
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// End:  
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