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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_scoreboard_fsm.v] - Blame information for rev 19

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//----------------------------------------------------------------------
//  Scoreboard FSM
//
// Keeps track of data regarding N items.  Allows multiple entities
// to track data about a particular item.  Supports masked writes,
// allowing only part of a record to be updated by a particular
// transaction.
//
// If masks are enabled, 
//
// Naming convention: c = consumer, p = producer, i = internal interface
//----------------------------------------------------------------------
//  Author: Guy Hutchison
//
// This block is uncopyrighted and released into the public domain.
//----------------------------------------------------------------------
 
// Clocking statement for synchronous blocks.  Default is for
// posedge clocking and positive async reset
`ifndef SDLIB_CLOCKING
 `define SDLIB_CLOCKING posedge clk or posedge reset
`endif
 
// delay unit for nonblocking assigns, default is to #1
`ifndef SDLIB_DELAY
 `define SDLIB_DELAY #1
`endif
 
module sd_scoreboard_fsm
  #(parameter width=8,
    parameter items=64,
    parameter use_txid=0,
    parameter use_mask=0,
    parameter txid_sz=2,
    parameter asz=$clog2(items))
  (input      clk,
   input      reset,
 
   input      ip_srdy,
   output reg     ip_drdy,
   input      ip_req_type, // 0=read, 1=write
   input [txid_sz-1:0] ip_txid,
   input [width-1:0] ip_mask,
   input [width-1:0] ip_data,
   input [asz-1:0]   ip_itemid,
 
   output reg     ic_srdy,
   input      ic_drdy,
   output reg [txid_sz-1:0] ic_txid,
   output reg [width-1:0]   ic_data,
 
   input [width-1:0]    d_out,
   output reg               wr_en,
   output reg               rd_en,
   output reg [width-1:0]   d_in,
   output reg [asz-1:0]     addr
   );
 
  localparam s_idle = 0, s_read = 1, s_rdmod = 2;
 
  reg [2:0]                 state, nxt_state;
  reg [txid_sz-1:0]         txid, nxt_txid;
 
  always @*
    begin
      ip_drdy = 0;
      ic_srdy = 0;
      ic_data = 0;
      wr_en = 0;
      rd_en = 0;
      d_in = 0;
      addr = ip_itemid;
      nxt_state = state;
      nxt_txid  = txid;
      if (use_txid)
        ic_txid = txid;
      else
        ic_txid = 0;
 
      nxt_state[s_read] = 0;
 
      if (state[s_idle])
        begin
          if (state[s_read] & !ic_drdy)
            begin
              // output is busy, stall
            end
          else if (ip_srdy & (ip_req_type==1))
            begin
              if ((use_mask==0) | (ip_mask=={width{1'b1}}))
                begin
                  ip_drdy = 1;
                  wr_en   = 1;
                  d_in    = ip_data;
                end
              else
                begin
                  rd_en = 1;
                  nxt_state[s_rdmod] = 1;
                  nxt_state[s_idle]  = 0;
                end
            end
          else if (ip_srdy & (ip_req_type==0))
            begin
              rd_en = 1;
              nxt_state[s_read] = 1;
              nxt_txid  = ip_txid;
              ip_drdy   = 1;
            end
        end // case: s_idle
 
      if (state[s_read])
        begin
          ic_srdy = 1;
          ic_data = d_out;
          if (!ic_drdy)
            begin
              nxt_state[s_read] = 1;
              //nxt_state[s_idle] = 1;
            end
        end // case: state[s_read]
 
      if (state[s_rdmod])
        begin
          ip_drdy = 1;
          d_in = (d_out & ~ip_mask) | (ip_data & ip_mask);
          wr_en   = 1;
 
          nxt_state[s_rdmod] = 0;
          nxt_state[s_idle]  = 1;
        end
    end // always @ *
 
 
  always @(`SDLIB_CLOCKING)
    begin
      if (reset)
        begin
          state <= `SDLIB_DELAY 1;
        end
      else
        begin
          state <= `SDLIB_DELAY nxt_state;
        end
    end // always @ (`SDLIB_CLOCKING)
 
  generate
    if (use_txid != 0)
      begin : gen_txid_hold
        always @(`SDLIB_CLOCKING)
          begin
            if (reset)
              begin
                txid  <= `SDLIB_DELAY 0;
              end
            else
              begin
                txid  <= `SDLIB_DELAY nxt_txid;
              end
          end // always @ (`SDLIB_CLOCKING)
      end // block: gen_txid_hold
  endgenerate
 
endmodule // sd_scoreboard_fsm

Line No.	Rev	Author	Line
1	18	ghutchis	`//----------------------------------------------------------------------`
2			`// Scoreboard FSM`
3			`//`
4			`// Keeps track of data regarding N items. Allows multiple entities`
5			`// to track data about a particular item. Supports masked writes,`
6			`// allowing only part of a record to be updated by a particular`
7			`// transaction.`
8			`//`
9			`// If masks are enabled,`
10			`//`
11			`// Naming convention: c = consumer, p = producer, i = internal interface`
12			`//----------------------------------------------------------------------`
13			`// Author: Guy Hutchison`
14			`//`
15			`// This block is uncopyrighted and released into the public domain.`
16			`//----------------------------------------------------------------------`
17
18			`// Clocking statement for synchronous blocks. Default is for`
19			`// posedge clocking and positive async reset`
20			`ifndef SDLIB_CLOCKING
21			`define SDLIB_CLOCKING posedge clk or posedge reset
22			`endif
23
24			`// delay unit for nonblocking assigns, default is to #1`
25			`ifndef SDLIB_DELAY
26			`define SDLIB_DELAY #1
27			`endif
28
29			`module sd_scoreboard_fsm`
30			`#(parameter width=8,`
31			`parameter items=64,`
32			`parameter use_txid=0,`
33			`parameter use_mask=0,`
34			`parameter txid_sz=2,`
35			`parameter asz=$clog2(items))`
36			`(input clk,`
37			`input reset,`
38
39			`input ip_srdy,`
40			`output reg ip_drdy,`
41			`input ip_req_type, // 0=read, 1=write`
42			`input [txid_sz-1:0] ip_txid,`
43			`input [width-1:0] ip_mask,`
44			`input [width-1:0] ip_data,`
45			`input [asz-1:0] ip_itemid,`
46
47			`output reg ic_srdy,`
48			`input ic_drdy,`
49			`output reg [txid_sz-1:0] ic_txid,`
50			`output reg [width-1:0] ic_data,`
51
52			`input [width-1:0] d_out,`
53			`output reg wr_en,`
54			`output reg rd_en,`
55			`output reg [width-1:0] d_in,`
56			`output reg [asz-1:0] addr`
57			`);`
58
59			`localparam s_idle = 0, s_read = 1, s_rdmod = 2;`
60
61			`reg [2:0] state, nxt_state;`
62			`reg [txid_sz-1:0] txid, nxt_txid;`
63
64			`always @*`
65			`begin`
66			`ip_drdy = 0;`
67			`ic_srdy = 0;`
68			`ic_data = 0;`
69			`wr_en = 0;`
70			`rd_en = 0;`
71			`d_in = 0;`
72			`addr = ip_itemid;`
73			`nxt_state = state;`
74			`nxt_txid = txid;`
75			`if (use_txid)`
76			`ic_txid = txid;`
77			`else`
78			`ic_txid = 0;`
79
80			`nxt_state[s_read] = 0;`
81
82			`if (state[s_idle])`
83			`begin`
84	19	ghutchis	`if (state[s_read] & !ic_drdy)`
85			`begin`
86			`// output is busy, stall`
87			`end`
88			`else if (ip_srdy & (ip_req_type==1))`
89	18	ghutchis	`begin`
90			`if ((use_mask==0) \| (ip_mask=={width{1'b1}}))`
91			`begin`
92			`ip_drdy = 1;`
93			`wr_en = 1;`
94			`d_in = ip_data;`
95			`end`
96			`else`
97			`begin`
98			`rd_en = 1;`
99			`nxt_state[s_rdmod] = 1;`
100			`nxt_state[s_idle] = 0;`
101			`end`
102			`end`
103	19	ghutchis	`else if (ip_srdy & (ip_req_type==0))`
104	18	ghutchis	`begin`
105			`rd_en = 1;`
106			`nxt_state[s_read] = 1;`
107			`nxt_txid = ip_txid;`
108			`ip_drdy = 1;`
109			`end`
110			`end // case: s_idle`
111
112			`if (state[s_read])`
113			`begin`
114			`ic_srdy = 1;`
115			`ic_data = d_out;`
116			`if (!ic_drdy)`
117			`begin`
118			`nxt_state[s_read] = 1;`
119			`//nxt_state[s_idle] = 1;`
120			`end`
121			`end // case: state[s_read]`
122
123			`if (state[s_rdmod])`
124			`begin`
125			`ip_drdy = 1;`
126			`d_in = (d_out & ~ip_mask) \| (ip_data & ip_mask);`
127			`wr_en = 1;`
128
129			`nxt_state[s_rdmod] = 0;`
130			`nxt_state[s_idle] = 1;`
131			`end`
132			`end // always @ *`
133
134
135			always @(`SDLIB_CLOCKING)
136			`begin`
137			`if (reset)`
138			`begin`
139			state <= `SDLIB_DELAY 1;
140			`end`
141			`else`
142			`begin`
143			state <= `SDLIB_DELAY nxt_state;
144			`end`
145			end // always @ (`SDLIB_CLOCKING)
146
147			`generate`
148			`if (use_txid != 0)`
149			`begin : gen_txid_hold`
150			always @(`SDLIB_CLOCKING)
151			`begin`
152			`if (reset)`
153			`begin`
154			txid <= `SDLIB_DELAY 0;
155			`end`
156			`else`
157			`begin`
158			txid <= `SDLIB_DELAY nxt_txid;
159			`end`
160			end // always @ (`SDLIB_CLOCKING)
161			`end // block: gen_txid_hold`
162			`endgenerate`
163
164			`endmodule // sd_scoreboard_fsm`

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[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [utility/] [sd_scoreboard_fsm.v] - Blame information for rev 19