OpenCores
URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [docs/] [getting.md] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 rafaelcalc
# Getting started
2
 
3
To start using Steel, follow these steps:
4
 
5
1. Import all files inside the **rtl** directory into your project
6
2. Instantiate the core into a Verilog/SystemVerilog module (an instantiation template is provided below)
7
3. Connect Steel to a clock source, a reset signal and memory. There is an interface to fetch instructions and another to read/write data, so we recommend a dual-port memory
8
 
9
There are also interfaces to request for interrupts and to update the time register. The signals of these interfaces must be hardwired to zero if unused.
10
 
11
```verilog
12
steel_top #(
13
 
14
    // You must provide a 32-bit value. If omitted the boot address is set to 0x00000000
15
    // ---------------------------------------------------------------------------------
16
 
17
    .BOOT_ADDRESS()
18
 
19
    ) core (
20
 
21
    // Clock source and reset
22
    // ---------------------------------------------------------------------------------
23
 
24
    .CLK(),         // System clock (input, required, 1-bit)
25
    .RESET(),       // System reset (input, required, 1-bit, synchronous, active high)
26
 
27
    // Instruction fetch interface
28
    // ---------------------------------------------------------------------------------
29
    .I_ADDR(),      // Instruction address (output, 32-bit)
30
    .INSTR(),       // Instruction data (input, required, 32-bit)
31
 
32
    // Data read/write interface
33
    // ---------------------------------------------------------------------------------
34
 
35
    .D_ADDR(),      // Data address (output, 32-bit)
36
    .DATA_IN(),     // Data read from memory (input, required, 32-bit)
37
    .DATA_OUT(),    // Data to write into memory (output, 32-bit)
38
    .WR_REQ(),      // Write enable (output, 1-bit)
39
    .WR_MASK(),     // Write byte mask (output, 4-bit)
40
 
41
    // Interrupt request interface (hardwire to zero if unused)
42
    // ---------------------------------------------------------------------------------
43
 
44
    .E_IRQ(),       // External interrupt request (optional, active high, 1-bit)
45
    .T_IRQ(),       // Timer interrupt request (optional, active high, 1-bit)
46
    .S_IRQ()        // Software interrupt request (optional, active high, 1-bit)
47
 
48
    // Time register update interface (hardwire to zero if unused)
49
    // ---------------------------------------------------------------------------------
50
 
51
    .REAL_TIME(),   // Value read from a real-time counter (optional, 64-bit)
52
 
53
);
54
```
55
 
56
Read the section [I/O signals](steelio.md) for more information about the signals above.

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.