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# Exceptions and interrupts
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## Supported exceptions and interrupts
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Steel supports the exceptions and interrupts shown in the table below. They are listed in descending priority order (the highest priority is at the top of the table). If two or more exceptions/interrupts occur at the same time, the one with the highest priority is taken.
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Exceptions always cause a trap to be taken. An interrupt will cause a trap only if enabled. Each type of interrupt has an interrupt-enable bit in the **mie** register. Interrupts are globally enable/disabled by setting the MIE bit of **mstatus** register.
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|  **Exception / Interrupt**               | ***mcause*** **interrupt bit**     | ***mcause*** **exception code**  |
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| :--------------------------------------- | ----------------: | ------------------: |
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| Machine external interrupt               | 1                 | 11                  |
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| Machine software interrupt               | 1                 | 3                   |
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| Machine timer interrupt                  | 1                 | 7                   |
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| Illegal instruction exception            | 0                 | 2                   |
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| Instruction address-misaligned exception | 0                 | 0                   |
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| Environment call from M-mode exception   | 0                 | 11                  |
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| Environment break exception              | 0                 | 3                   |
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| Store address-misaligned exception       | 0                 | 6                   |
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| Load address-misaligned exception        | 0                 | 4                   |
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## Trap handling in Steel
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Exceptions and interrupts are handled by a trap handler routine stored in memory. The address of the trap handler first instruction is configured using the **mtvec** register. Steel supports both direct and vectorized interrupt modes.
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When a trap is taken, the core proceeds as follows:
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* the address of the interrupted instruction (or the instruction that encountered the exception) is saved in the **mepc** register;
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* the value of the **mtval** register is set to:
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    * the misaligned address that caused the exception for all types of address-misaligned exceptions, or
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    * zero otherwise;
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* the value of the **mstatus** MIE bit is saved in the MPIE field and then set to zero;
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* the program counter is set to the address of the trap handler first instruction.
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The **mret** instruction is used to return from traps. When executed, the core proceeds as follows:
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* the value of the **mstatus** MPIE bit is saved in the MIE field and then set to one;
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* the program counter is set to the value of **mepc** register.
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## Nested interrupts capability
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The core globally disables new interrupts when takes into a trap. The trap handler can re-enable interrupts by setting the **mstatus** MIE bit to one, thus enabling nested interrupts. To return from nested traps, the trap handler must stack and manage the values of the **mepc** register in memory.

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