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[/] [rtl/] [bench/] [tb_integer_file.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
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// 
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// Create Date: 03.04.2020 18:35:35
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// Module Name: tb_integer_file
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// Project Name: Steel Core
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// Description: 32-bit Integer Register File testbench
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// 
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// Dependencies: globals.vh
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//               integer_file.v
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "../globals.vh"
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module tb_integer_file();
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    reg CLK;
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    reg [4:0] RS_1_ADDR;
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    reg [4:0] RS_2_ADDR;
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    wire [31:0] RS_1;
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    wire [31:0] RS_2;
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    reg [4:0] RD_ADDR;
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    reg WR_EN;
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    reg [31:0] RD;
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    integer_file dut(
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        .CLK(               CLK),
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        .RS_1_ADDR(         RS_1_ADDR),
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        .RS_2_ADDR(         RS_2_ADDR),
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        .RD_ADDR(           RD_ADDR),
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        .RS_1(              RS_1),
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        .RS_2(              RS_2),
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        .WR_EN(             WR_EN),
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        .RD(                RD)
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    );
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    integer i;
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    always
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    begin
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        #10 CLK = !CLK;
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    end
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    initial
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    begin
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        $display("Testing Integer Register File...");
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        CLK = 1'b0;
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        RS_1_ADDR = 5'b00000;
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        RS_2_ADDR = 5'b00000;
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        RD_ADDR = 5'b00000;
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        WR_EN = 1'b0;
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        RD = 32'b0;
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        $display("Testing values on power up...");
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        for(i = 0; i < 32; i=i+1)
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        begin
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            RS_1_ADDR = i[4:0];
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            #20;
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            if(RS_1 != 32'h00000000)
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            begin
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                $display("FAIL. Check the results.");
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                $finish;
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            end
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        end
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        $display("Power up values OK.");
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        $display("Testing write operation...");
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        for(i = 0; i < 32; i=i+1)
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        begin
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            RD_ADDR = i[4:0];
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            WR_EN = 1'b1;
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            RD = $random;
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            #20;
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            WR_EN = 1'b0;
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            RS_1_ADDR = RD_ADDR;
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            RS_2_ADDR = RD_ADDR;
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            #20;
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            if(RD_ADDR == 5'b00000)
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            begin
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                if(RS_1 != 32'h00000000)
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                begin
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                    $display("FAIL. Check the results.");
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                    $finish;
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                end
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                if(RS_2 != 32'h00000000)
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                begin
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                    $display("FAIL. Check the results.");
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                    $finish;
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                end
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            end
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            if(RD_ADDR != 5'b00000)
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            begin
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                if(RS_1 != RD)
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                begin
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                    $display("FAIL. Check the results.");
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                    $finish;
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                end
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                if(RS_2 != RD)
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                begin
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                    $display("FAIL. Check the results.");
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                    $finish;
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                end
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            end
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        end
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        $display("Write operation seems to work.");
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        $display("Integer Register File successfully tested.");
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    end
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endmodule

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