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[/] [rtl/] [load_unit.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
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// 
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// Create Date: 26.04.2020 20:30:54
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// Module Name: load_unit
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// Project Name: Steel Core 
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// Description: Sign extends the data read from memory
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// 
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// Dependencies: globals.vh
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "globals.vh"
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module load_unit(
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    input wire [1:0] LOAD_SIZE,
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    input wire LOAD_UNSIGNED,
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    input wire [31:0] DATA_IN,
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    input wire [1:0] IADDER_OUT_1_TO_0,
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    output reg [31:0] OUTPUT
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    );
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    reg [7:0] byte;
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    reg [15:0] half;
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    wire [23:0] byte_ext;
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    wire [15:0] half_ext;
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    always @*
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    begin
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        case(LOAD_SIZE)
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            2'b00: OUTPUT = {byte_ext, byte};
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            2'b01: OUTPUT = {half_ext, half};
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            2'b10: OUTPUT = DATA_IN;
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            2'b11: OUTPUT = DATA_IN;
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        endcase
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    end
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    always @*
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    begin
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        case(IADDER_OUT_1_TO_0)
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            2'b00: byte = DATA_IN[7:0];
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            2'b01: byte = DATA_IN[15:8];
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            2'b10: byte = DATA_IN[23:16];
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            2'b11: byte = DATA_IN[31:24];
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        endcase
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    end
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    always @*
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    begin
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        case(IADDER_OUT_1_TO_0[1])
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            1'b0: half = DATA_IN[15:0];
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            1'b1: half = DATA_IN[31:16];
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        endcase
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    end
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    assign byte_ext = LOAD_UNSIGNED == 1'b1 ? 24'b0 : {24{byte[7]}};
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    assign half_ext = LOAD_UNSIGNED == 1'b1 ? 16'b0 : {16{half[15]}};
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endmodule

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