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[/] [rtl/] [store_unit.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com)
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// 
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// Create Date: 02.06.2020 01:28:57
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// Module Name: store_unit
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// Project Name: Steel Core 
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// Description: Controls the data memory interface
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// 
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// Dependencies: globals.vh
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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`include "globals.vh"
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module store_unit(
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    input wire [1:0] FUNCT3,
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    input wire [31:0] IADDER_OUT,
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    input wire [31:0] RS2,
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    input wire MEM_WR_REQ,
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    output reg [31:0] DATA_OUT,
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    output wire [31:0] D_ADDR,
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    output reg [3:0] WR_MASK,
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    output wire WR_REQ
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    );
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    reg [3:0] half_wr_mask;
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    reg [3:0] byte_wr_mask;
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    reg [31:0] half_dout;
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    reg [31:0] byte_dout;
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    assign D_ADDR = {IADDER_OUT[31:2], 2'b0};
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    assign WR_REQ = MEM_WR_REQ;
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    always @*
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    begin
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        case(FUNCT3[1:0])
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            2'b00: WR_MASK = byte_wr_mask;
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            2'b01: WR_MASK = half_wr_mask;
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            2'b10: WR_MASK = {4{MEM_WR_REQ}};
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            2'b11: WR_MASK = {4{MEM_WR_REQ}};
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        endcase
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    end
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    always @*
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    begin
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        case(FUNCT3[1:0])
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            2'b00: DATA_OUT = byte_dout;
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            2'b01: DATA_OUT = half_dout;
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            2'b10: DATA_OUT = RS2;
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            2'b11: DATA_OUT = RS2;
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        endcase
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    end
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    always @*
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    begin
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        case(IADDER_OUT[1:0])
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            2'b00: byte_dout = {24'b0, RS2[7:0]};
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            2'b01: byte_dout = {16'b0, RS2[7:0], 8'b0};
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            2'b10: byte_dout = {8'b0, RS2[7:0], 16'b0};
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            2'b11: byte_dout = {RS2[7:0], 24'b0};
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        endcase
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    end
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    always @*
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    begin
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        case(IADDER_OUT[1:0])
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            2'b00: byte_wr_mask = {3'b0, MEM_WR_REQ};
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            2'b01: byte_wr_mask = {2'b0, MEM_WR_REQ, 1'b0};
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            2'b10: byte_wr_mask = {1'b0, MEM_WR_REQ, 2'b0};
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            2'b11: byte_wr_mask = {MEM_WR_REQ, 3'b0};
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        endcase
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    end
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    always @*
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    begin
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        case(IADDER_OUT[1])
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            1'b0: half_dout = {16'b0, RS2[15:0]};
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            1'b1: half_dout = {RS2[15:0], 16'b0};
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        endcase
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    end
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    always @*
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    begin
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        case(IADDER_OUT[1])
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            1'b0: half_wr_mask = {2'b0, {2{MEM_WR_REQ}}};
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            1'b1: half_wr_mask = {{2{MEM_WR_REQ}}, 2'b0};
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        endcase
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    end
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endmodule

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