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[/] [soc/] [bench/] [tb_soc_top.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
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// 
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// Create Date: 11.07.2020 14:55:12
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// Module Name: tb_soc_top
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// Project Name: Steel SoC 
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// Description: Example SoC testbench 
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// 
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// Dependencies: globals.vh
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//               machine_control.v
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//               alu.v
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//               integer_file.v
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//               branch_unit.v
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//               decoder.v
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//               csr_file.v
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//               imm_generator.v
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//               load_unit.v
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//               store_unit.v
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//               steel_top.v
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//               bus_arbiter.v
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//               ram.v
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//               uart_tx.v
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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module tb_soc_top();
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    reg CLK;
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    reg RESET;
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    wire UART_TX;
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    soc_top #(
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        .BOOT_ADDRESS(32'h00000018)
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        ) dut (
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        .CLK(CLK),
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        .RESET(RESET),
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        .UART_TX(UART_TX)
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    );
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    always #10 CLK = !CLK;
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    // The purpose of this testbench is to observe the UART waveform
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    initial
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    begin
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        CLK = 1'b0;
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        RESET = 1'b1;
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        #100;
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        RESET = 1'b0;
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        $stop();
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    end
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endmodule

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