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[/] [soc/] [bus_arbiter.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
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// 
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// Create Date: 06.07.2020 21:30:07
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// Module Name: bus_arbiter
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// Project Name: Steel SoC 
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// Description: Bus arbiter 
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// 
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// Dependencies: -
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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module bus_arbiter(
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    input wire CLK,
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    input wire RESET,
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    // Connection with the core
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    input wire [31:0] D_ADDR,
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    input wire [31:0] DATA_OUT,
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    input wire WR_REQ,
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    input wire [3:0] WR_MASK,
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    output wire [31:0] DATA_IN,
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    // PORT #1 - Connected to UART
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    output wire [31:0] D_ADDR_1,
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    output wire [31:0] DATA_OUT_1,
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    output wire WR_REQ_1,
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    output wire [3:0] WR_MASK_1,
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    input wire [31:0] DATA_IN_1,
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    // PORT #2 - Connected to MAIN MEMORY
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    output wire [31:0] D_ADDR_2,
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    output wire [31:0] DATA_OUT_2,
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    output wire WR_REQ_2,
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    output wire [3:0] WR_MASK_2,
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    input wire [31:0] DATA_IN_2
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    );
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    reg last_access;
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    wire uart_access = D_ADDR[31:12] == 20'h00010;
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    always @(posedge CLK)
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    begin
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        if(RESET) last_access <= 1'b0;
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        else last_access <= uart_access;
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    end
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    assign D_ADDR_1 = uart_access ? D_ADDR : 32'b0;
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    assign DATA_OUT_1 = uart_access ? DATA_OUT : 32'b0;
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    assign WR_REQ_1 = uart_access ? WR_REQ : 1'b0;
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    assign WR_MASK_1 = uart_access ? WR_MASK : 4'b0;
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    assign D_ADDR_2 = ~uart_access ? D_ADDR : 32'b0;
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    assign DATA_OUT_2 = ~uart_access ? DATA_OUT : 32'b0;
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    assign WR_REQ_2 = ~uart_access ? WR_REQ : 1'b0;
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    assign WR_MASK_2 = ~uart_access ? WR_MASK : 4'b0;
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    assign DATA_IN = last_access ? DATA_IN_1 : DATA_IN_2;
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endmodule

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