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[/] [soc/] [uart_tx.v] - Blame information for rev 11

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1 11 rafaelcalc
//////////////////////////////////////////////////////////////////////////////////
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// Engineer: Rafael de Oliveira Calçada (rafaelcalcada@gmail.com) 
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// 
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// Create Date: 05.08.2020 13:52:21
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// Module Name: uart_tx
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// Project Name: Steel SoC 
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// Description: UART transmitter (9600 baud, 1 stop bit, no parity, no control)
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// 
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// Dependencies: -
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// 
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// Version 0.01
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// 
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//////////////////////////////////////////////////////////////////////////////////
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/*********************************************************************************
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MIT License
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Copyright (c) 2020 Rafael de Oliveira Calçada
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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********************************************************************************/
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`timescale 1ns / 1ps
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module uart_tx(
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    input wire CLK,
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    input wire [7:0] WDATA,
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    input wire WR_EN,
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    output wire [31:0] RDATA,
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    output reg TX
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    );
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    // Regs and wires
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    wire done;
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    reg [9:0] data;
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    reg [14:0] timer;
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    reg [3:0] index;
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    // States
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    parameter STATE_READY   = 2'b01;
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    parameter STATE_LOAD    = 2'b10;
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    parameter STATE_SEND    = 2'b00;
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    // State registers
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    reg [2:0] tx_state;
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    // State update    
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    always @(posedge CLK)
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    begin
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        case (tx_state)
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            STATE_READY:
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            begin
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                if(WR_EN == 1'b1) tx_state <= STATE_LOAD;
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                else tx_state <= STATE_READY;
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            end
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            STATE_LOAD: tx_state <= STATE_SEND;
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            STATE_SEND:
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            begin
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                if(done)
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                begin
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                    if(index == 10) tx_state <= STATE_READY;
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                    else tx_state <= STATE_LOAD;
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                end
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            end
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            default: tx_state <= STATE_READY;
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        endcase
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    end
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    // Timer
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    always @(posedge CLK)
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    begin
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        if(tx_state == STATE_READY) timer <= 15'b0;
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        else if(done) timer <= 15'b0;
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        else timer <= timer + 1;
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    end
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    assign done = (timer == 5208) ? 1'b1 : 1'b0;
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    // Data index update    
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    always @(posedge CLK)
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    begin
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        if(tx_state == STATE_READY) index <= 1'b0;
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        else if(tx_state == STATE_LOAD) index <= index + 1;
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    end
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    // Data update
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    always @(posedge CLK)
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    begin
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        if(tx_state == STATE_READY && WR_EN == 1'b1) data <= {1'b1, WDATA, 1'b0};
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    end
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    // Output generation
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    always @(posedge CLK)
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    begin
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        if(tx_state == STATE_READY) TX <= 1'b1;
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        else if(tx_state == STATE_LOAD) TX <= data[index];
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        else TX <= TX;
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    end
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    // Output assignments
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    assign RDATA = {31'b0, tx_state[0]};
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endmodule

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