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[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [elaborate.log] - Blame information for rev 11

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Line No. Rev Author Line
1 11 rafaelcalc
Vivado Simulator 2019.2
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Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
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Running: /home/rafa/Xilinx/Vivado/2019.2/bin/unwrapped/lnx64.o/xelab -wto b8561a63f69e41d98a2e12d383a11daf --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_compliance_behav xil_defaultlib.tb_compliance xil_defaultlib.glbl -log elaborate.log
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Using 8 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module xil_defaultlib.store_unit
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Compiling module xil_defaultlib.decoder
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Compiling module xil_defaultlib.imm_generator
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Compiling module xil_defaultlib.branch_unit
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Compiling module xil_defaultlib.integer_file
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Compiling module xil_defaultlib.csr_file
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Compiling module xil_defaultlib.machine_control
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Compiling module xil_defaultlib.load_unit
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Compiling module xil_defaultlib.alu
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Compiling module xil_defaultlib.steel_top
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Compiling module xil_defaultlib.tb_compliance
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot tb_compliance_behav

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