URL https://opencores.org/ocsvn/steelcore/steelcore/trunk

Subversion Repositories steelcore

[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [tb_soc_top_vlog.prj] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	rafaelcalc	`# compile verilog/system verilog design source files`
2			`verilog xil_defaultlib \`
3			`"../../../../../rtl/alu.v" \`
4			`"../../../../../rtl/branch_unit.v" \`
5			`"../../../../../soc/bus_arbiter.v" \`
6			`"../../../../../rtl/csr_file.v" \`
7			`"../../../../../rtl/decoder.v" \`
8			`"../../../../../rtl/imm_generator.v" \`
9			`"../../../../../rtl/integer_file.v" \`
10			`"../../../../../rtl/load_unit.v" \`
11			`"../../../../../rtl/machine_control.v" \`
12			`"../../../../../soc/ram.v" \`
13			`"../../../../../soc/soc_top.v" \`
14			`"../../../../../rtl/steel_top.v" \`
15			`"../../../../../rtl/store_unit.v" \`
16			`"../../../../../soc/uart_tx.v" \`
17			`"../../../../../soc/bench/tb_soc_top.v" \`
18
19			`# compile glbl module`
20			`verilog xil_defaultlib "glbl.v"`
21
22			`# Do not sort compile order`
23			`nosort`