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[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [tb_soc_top_vlog.prj] - Blame information for rev 11

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1 11 rafaelcalc
# compile verilog/system verilog design source files
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verilog xil_defaultlib  \
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"../../../../../rtl/alu.v" \
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"../../../../../rtl/branch_unit.v" \
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"../../../../../soc/bus_arbiter.v" \
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"../../../../../rtl/csr_file.v" \
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"../../../../../rtl/decoder.v" \
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"../../../../../rtl/imm_generator.v" \
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"../../../../../rtl/integer_file.v" \
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"../../../../../rtl/load_unit.v" \
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"../../../../../rtl/machine_control.v" \
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"../../../../../soc/ram.v" \
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"../../../../../soc/soc_top.v" \
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"../../../../../rtl/steel_top.v" \
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"../../../../../rtl/store_unit.v" \
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"../../../../../soc/uart_tx.v" \
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"../../../../../soc/bench/tb_soc_top.v" \
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# compile glbl module
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verilog xil_defaultlib "glbl.v"
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# Do not sort compile order
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nosort

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