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[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [xsim.dir/] [tb_compliance_behav/] [xsimSettings.ini] - Blame information for rev 11

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Line No. Rev Author Line
1 11 rafaelcalc
[General]
2
ARRAY_DISPLAY_LIMIT=512
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RADIX=hex
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TIME_UNIT=ns
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TRACE_LIMIT=2147483647
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VHDL_ENTITY_SCOPE_FILTER=true
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VHDL_PACKAGE_SCOPE_FILTER=false
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VHDL_BLOCK_SCOPE_FILTER=true
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VHDL_PROCESS_SCOPE_FILTER=false
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VHDL_PROCEDURE_SCOPE_FILTER=false
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VERILOG_MODULE_SCOPE_FILTER=true
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VERILOG_PACKAGE_SCOPE_FILTER=false
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VERILOG_BLOCK_SCOPE_FILTER=false
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VERILOG_TASK_SCOPE_FILTER=false
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VERILOG_PROCESS_SCOPE_FILTER=false
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INPUT_OBJECT_FILTER=true
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OUTPUT_OBJECT_FILTER=true
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INOUT_OBJECT_FILTER=true
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INTERNAL_OBJECT_FILTER=true
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CONSTANT_OBJECT_FILTER=true
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VARIABLE_OBJECT_FILTER=true
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INPUT_PROTOINST_FILTER=true
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OUTPUT_PROTOINST_FILTER=true
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INOUT_PROTOINST_FILTER=true
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INTERNAL_PROTOINST_FILTER=true
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CONSTANT_PROTOINST_FILTER=true
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VARIABLE_PROTOINST_FILTER=true
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SCOPE_NAME_COLUMN_WIDTH=132
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SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75
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SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
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OBJECT_NAME_COLUMN_WIDTH=207
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OBJECT_VALUE_COLUMN_WIDTH=161
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OBJECT_DATA_TYPE_COLUMN_WIDTH=75
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PROCESS_NAME_COLUMN_WIDTH=0
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PROCESS_TYPE_COLUMN_WIDTH=0
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FRAME_INDEX_COLUMN_WIDTH=0
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FRAME_NAME_COLUMN_WIDTH=0
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FRAME_FILE_NAME_COLUMN_WIDTH=0
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FRAME_LINE_NUM_COLUMN_WIDTH=0
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LOCAL_NAME_COLUMN_WIDTH=0
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LOCAL_VALUE_COLUMN_WIDTH=0
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LOCAL_DATA_TYPEPROTO_NAME_COLUMN_WIDTH=0
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PROTO_VALUE_COLUMN_WIDTH=0
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PROTO_DATA_TYPE_COLUMN_WIDTH=0
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INPUT_LOCAL_FILTER=1
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OUTPUT_LOCAL_FILTER=1
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INOUT_LOCAL_FILTER=1
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INTERNAL_LOCAL_FILTER=1
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CONSTANT_LOCAL_FILTER=1
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VARIABLE_LOCAL_FILTER=1

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