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Subversion Repositories steelcore

[/] [vivado/] [steel-core.sim/] [sim_1/] [behav/] [xsim/] [xsim.dir/] [xil_defaultlib/] [xil_defaultlib.rlx] - Blame information for rev 11

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Line No. Rev Author Line
1 11 rafaelcalc
0.6
2
2019.2
3
Nov  6 2019
4
21:42:20
5
/home/rafa/ufrgs/steel-core/rtl/alu.v,1596913227,verilog,,/home/rafa/ufrgs/steel-core/rtl/branch_unit.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,alu,,,,,,,,
6
/home/rafa/ufrgs/steel-core/rtl/bench/tb_compliance.v,1602395046,verilog,,,/home/rafa/ufrgs/steel-core/rtl/globals.vh,tb_compliance,,,,,,,,
7
/home/rafa/ufrgs/steel-core/rtl/branch_unit.v,1596912912,verilog,,/home/rafa/ufrgs/steel-core/rtl/csr_file.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,branch_unit,,,,,,,,
8
/home/rafa/ufrgs/steel-core/rtl/csr_file.v,1596913042,verilog,,/home/rafa/ufrgs/steel-core/rtl/decoder.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,csr_file,,,,,,,,
9
/home/rafa/ufrgs/steel-core/rtl/decoder.v,1596912796,verilog,,/home/rafa/ufrgs/steel-core/rtl/imm_generator.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,decoder,,,,,,,,
10
/home/rafa/ufrgs/steel-core/rtl/globals.vh,1596912108,verilog,,,,,,,,,,,,
11
/home/rafa/ufrgs/steel-core/rtl/imm_generator.v,1596912869,verilog,,/home/rafa/ufrgs/steel-core/rtl/integer_file.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,imm_generator,,,,,,,,
12
/home/rafa/ufrgs/steel-core/rtl/integer_file.v,1596913004,verilog,,/home/rafa/ufrgs/steel-core/rtl/load_unit.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,integer_file,,,,,,,,
13
/home/rafa/ufrgs/steel-core/rtl/load_unit.v,1596913198,verilog,,/home/rafa/ufrgs/steel-core/rtl/machine_control.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,load_unit,,,,,,,,
14
/home/rafa/ufrgs/steel-core/rtl/machine_control.v,1596913164,verilog,,/home/rafa/ufrgs/steel-core/rtl/steel_top.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,machine_control,,,,,,,,
15
/home/rafa/ufrgs/steel-core/rtl/steel_top.v,1596912541,verilog,,/home/rafa/ufrgs/steel-core/rtl/store_unit.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,steel_top,,,,,,,,
16
/home/rafa/ufrgs/steel-core/rtl/store_unit.v,1596912778,verilog,,/home/rafa/ufrgs/steel-core/rtl/bench/tb_compliance.v,/home/rafa/ufrgs/steel-core/rtl/globals.vh,store_unit,,,,,,,,
17
/home/rafa/ufrgs/steel-core/soc/bench/tb_soc_top.v,1602025651,verilog,,,,tb_soc_top,,,,,,,,
18
/home/rafa/ufrgs/steel-core/soc/bus_arbiter.v,1597156155,verilog,,/home/rafa/ufrgs/steel-core/rtl/csr_file.v,,bus_arbiter,,,,,,,,
19
/home/rafa/ufrgs/steel-core/soc/ram.v,1602024348,verilog,,/home/rafa/ufrgs/steel-core/soc/soc_top.v,,ram,,,,,,,,
20
/home/rafa/ufrgs/steel-core/soc/soc_top.v,1602024387,verilog,,/home/rafa/ufrgs/steel-core/rtl/steel_top.v,,soc_top,,,,,,,,
21
/home/rafa/ufrgs/steel-core/soc/uart_tx.v,1596912658,verilog,,/home/rafa/ufrgs/steel-core/soc/bench/tb_soc_top.v,,uart_tx,,,,,,,,
22
/home/rafa/ufrgs/steel-core/vivado/steel-core.sim/sim_1/behav/xsim/glbl.v,1573089660,verilog,,,,glbl,,,,,,,,

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